1 /* 2 * Virtio GPU Device 3 * 4 * Copyright Red Hat, Inc. 2013-2014 5 * 6 * Authors: 7 * Dave Airlie <airlied@redhat.com> 8 * Gerd Hoffmann <kraxel@redhat.com> 9 * 10 * This work is licensed under the terms of the GNU GPL, version 2. 11 * See the COPYING file in the top-level directory. 12 */ 13 14 #ifndef HW_VIRTIO_GPU_H 15 #define HW_VIRTIO_GPU_H 16 17 #include "qemu/queue.h" 18 #include "ui/qemu-pixman.h" 19 #include "ui/console.h" 20 #include "hw/virtio/virtio.h" 21 #include "qemu/log.h" 22 #include "sysemu/vhost-user-backend.h" 23 24 #include "standard-headers/linux/virtio_gpu.h" 25 #include "standard-headers/linux/virtio_ids.h" 26 #include "qom/object.h" 27 28 #define TYPE_VIRTIO_GPU_BASE "virtio-gpu-base" 29 OBJECT_DECLARE_TYPE(VirtIOGPUBase, VirtIOGPUBaseClass, 30 VIRTIO_GPU_BASE) 31 32 #define TYPE_VIRTIO_GPU "virtio-gpu-device" 33 OBJECT_DECLARE_TYPE(VirtIOGPU, VirtIOGPUClass, VIRTIO_GPU) 34 35 #define TYPE_VIRTIO_GPU_GL "virtio-gpu-gl-device" 36 OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPUGL, VIRTIO_GPU_GL) 37 38 #define TYPE_VHOST_USER_GPU "vhost-user-gpu" 39 OBJECT_DECLARE_SIMPLE_TYPE(VhostUserGPU, VHOST_USER_GPU) 40 41 struct virtio_gpu_simple_resource { 42 uint32_t resource_id; 43 uint32_t width; 44 uint32_t height; 45 uint32_t format; 46 uint64_t *addrs; 47 struct iovec *iov; 48 unsigned int iov_cnt; 49 uint32_t scanout_bitmask; 50 pixman_image_t *image; 51 #ifdef WIN32 52 HANDLE handle; 53 #endif 54 uint64_t hostmem; 55 56 uint64_t blob_size; 57 void *blob; 58 int dmabuf_fd; 59 uint8_t *remapped; 60 61 QTAILQ_ENTRY(virtio_gpu_simple_resource) next; 62 }; 63 64 struct virtio_gpu_framebuffer { 65 pixman_format_code_t format; 66 uint32_t bytes_pp; 67 uint32_t width, height; 68 uint32_t stride; 69 uint32_t offset; 70 }; 71 72 struct virtio_gpu_scanout { 73 QemuConsole *con; 74 DisplaySurface *ds; 75 uint32_t width, height; 76 int x, y; 77 int invalidate; 78 uint32_t resource_id; 79 struct virtio_gpu_update_cursor cursor; 80 QEMUCursor *current_cursor; 81 }; 82 83 struct virtio_gpu_requested_state { 84 uint16_t width_mm, height_mm; 85 uint32_t width, height; 86 uint32_t refresh_rate; 87 int x, y; 88 }; 89 90 enum virtio_gpu_base_conf_flags { 91 VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1, 92 VIRTIO_GPU_FLAG_STATS_ENABLED, 93 VIRTIO_GPU_FLAG_EDID_ENABLED, 94 VIRTIO_GPU_FLAG_DMABUF_ENABLED, 95 VIRTIO_GPU_FLAG_BLOB_ENABLED, 96 }; 97 98 #define virtio_gpu_virgl_enabled(_cfg) \ 99 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED)) 100 #define virtio_gpu_stats_enabled(_cfg) \ 101 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED)) 102 #define virtio_gpu_edid_enabled(_cfg) \ 103 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_EDID_ENABLED)) 104 #define virtio_gpu_dmabuf_enabled(_cfg) \ 105 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_DMABUF_ENABLED)) 106 #define virtio_gpu_blob_enabled(_cfg) \ 107 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_BLOB_ENABLED)) 108 109 struct virtio_gpu_base_conf { 110 uint32_t max_outputs; 111 uint32_t flags; 112 uint32_t xres; 113 uint32_t yres; 114 }; 115 116 struct virtio_gpu_ctrl_command { 117 VirtQueueElement elem; 118 VirtQueue *vq; 119 struct virtio_gpu_ctrl_hdr cmd_hdr; 120 uint32_t error; 121 bool finished; 122 QTAILQ_ENTRY(virtio_gpu_ctrl_command) next; 123 }; 124 125 struct VirtIOGPUBase { 126 VirtIODevice parent_obj; 127 128 Error *migration_blocker; 129 130 struct virtio_gpu_base_conf conf; 131 struct virtio_gpu_config virtio_config; 132 const GraphicHwOps *hw_ops; 133 134 int renderer_blocked; 135 int enable; 136 137 struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS]; 138 139 int enabled_output_bitmask; 140 struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS]; 141 }; 142 143 struct VirtIOGPUBaseClass { 144 VirtioDeviceClass parent; 145 146 void (*gl_flushed)(VirtIOGPUBase *g); 147 }; 148 149 #define VIRTIO_GPU_BASE_PROPERTIES(_state, _conf) \ 150 DEFINE_PROP_UINT32("max_outputs", _state, _conf.max_outputs, 1), \ 151 DEFINE_PROP_BIT("edid", _state, _conf.flags, \ 152 VIRTIO_GPU_FLAG_EDID_ENABLED, true), \ 153 DEFINE_PROP_UINT32("xres", _state, _conf.xres, 1280), \ 154 DEFINE_PROP_UINT32("yres", _state, _conf.yres, 800) 155 156 typedef struct VGPUDMABuf { 157 QemuDmaBuf buf; 158 uint32_t scanout_id; 159 QTAILQ_ENTRY(VGPUDMABuf) next; 160 } VGPUDMABuf; 161 162 struct VirtIOGPU { 163 VirtIOGPUBase parent_obj; 164 165 uint64_t conf_max_hostmem; 166 167 VirtQueue *ctrl_vq; 168 VirtQueue *cursor_vq; 169 170 QEMUBH *ctrl_bh; 171 QEMUBH *cursor_bh; 172 173 QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist; 174 QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq; 175 QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq; 176 177 uint64_t hostmem; 178 179 bool processing_cmdq; 180 QEMUTimer *fence_poll; 181 QEMUTimer *print_stats; 182 183 uint32_t inflight; 184 struct { 185 uint32_t max_inflight; 186 uint32_t requests; 187 uint32_t req_3d; 188 uint32_t bytes_3d; 189 } stats; 190 191 struct { 192 QTAILQ_HEAD(, VGPUDMABuf) bufs; 193 VGPUDMABuf *primary[VIRTIO_GPU_MAX_SCANOUTS]; 194 } dmabuf; 195 }; 196 197 struct VirtIOGPUClass { 198 VirtIOGPUBaseClass parent; 199 200 void (*handle_ctrl)(VirtIODevice *vdev, VirtQueue *vq); 201 void (*process_cmd)(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd); 202 void (*update_cursor_data)(VirtIOGPU *g, 203 struct virtio_gpu_scanout *s, 204 uint32_t resource_id); 205 }; 206 207 struct VirtIOGPUGL { 208 struct VirtIOGPU parent_obj; 209 210 bool renderer_inited; 211 bool renderer_reset; 212 }; 213 214 struct VhostUserGPU { 215 VirtIOGPUBase parent_obj; 216 217 VhostUserBackend *vhost; 218 int vhost_gpu_fd; /* closed by the chardev */ 219 CharBackend vhost_chr; 220 QemuDmaBuf dmabuf[VIRTIO_GPU_MAX_SCANOUTS]; 221 bool backend_blocked; 222 }; 223 224 #define VIRTIO_GPU_FILL_CMD(out) do { \ 225 size_t s; \ 226 s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \ 227 &out, sizeof(out)); \ 228 if (s != sizeof(out)) { \ 229 qemu_log_mask(LOG_GUEST_ERROR, \ 230 "%s: command size incorrect %zu vs %zu\n", \ 231 __func__, s, sizeof(out)); \ 232 return; \ 233 } \ 234 } while (0) 235 236 /* virtio-gpu-base.c */ 237 bool virtio_gpu_base_device_realize(DeviceState *qdev, 238 VirtIOHandleOutput ctrl_cb, 239 VirtIOHandleOutput cursor_cb, 240 Error **errp); 241 void virtio_gpu_base_reset(VirtIOGPUBase *g); 242 void virtio_gpu_base_fill_display_info(VirtIOGPUBase *g, 243 struct virtio_gpu_resp_display_info *dpy_info); 244 245 void virtio_gpu_base_generate_edid(VirtIOGPUBase *g, int scanout, 246 struct virtio_gpu_resp_edid *edid); 247 /* virtio-gpu.c */ 248 void virtio_gpu_ctrl_response(VirtIOGPU *g, 249 struct virtio_gpu_ctrl_command *cmd, 250 struct virtio_gpu_ctrl_hdr *resp, 251 size_t resp_len); 252 void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g, 253 struct virtio_gpu_ctrl_command *cmd, 254 enum virtio_gpu_ctrl_type type); 255 void virtio_gpu_get_display_info(VirtIOGPU *g, 256 struct virtio_gpu_ctrl_command *cmd); 257 void virtio_gpu_get_edid(VirtIOGPU *g, 258 struct virtio_gpu_ctrl_command *cmd); 259 int virtio_gpu_create_mapping_iov(VirtIOGPU *g, 260 uint32_t nr_entries, uint32_t offset, 261 struct virtio_gpu_ctrl_command *cmd, 262 uint64_t **addr, struct iovec **iov, 263 uint32_t *niov); 264 void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g, 265 struct iovec *iov, uint32_t count); 266 void virtio_gpu_process_cmdq(VirtIOGPU *g); 267 void virtio_gpu_device_realize(DeviceState *qdev, Error **errp); 268 void virtio_gpu_reset(VirtIODevice *vdev); 269 void virtio_gpu_simple_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd); 270 void virtio_gpu_update_cursor_data(VirtIOGPU *g, 271 struct virtio_gpu_scanout *s, 272 uint32_t resource_id); 273 274 /* virtio-gpu-udmabuf.c */ 275 bool virtio_gpu_have_udmabuf(void); 276 void virtio_gpu_init_udmabuf(struct virtio_gpu_simple_resource *res); 277 void virtio_gpu_fini_udmabuf(struct virtio_gpu_simple_resource *res); 278 int virtio_gpu_update_dmabuf(VirtIOGPU *g, 279 uint32_t scanout_id, 280 struct virtio_gpu_simple_resource *res, 281 struct virtio_gpu_framebuffer *fb, 282 struct virtio_gpu_rect *r); 283 284 /* virtio-gpu-3d.c */ 285 void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, 286 struct virtio_gpu_ctrl_command *cmd); 287 void virtio_gpu_virgl_fence_poll(VirtIOGPU *g); 288 void virtio_gpu_virgl_reset_scanout(VirtIOGPU *g); 289 void virtio_gpu_virgl_reset(VirtIOGPU *g); 290 int virtio_gpu_virgl_init(VirtIOGPU *g); 291 int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g); 292 293 #endif 294