1 /* 2 * Virtio GPU Device 3 * 4 * Copyright Red Hat, Inc. 2013-2014 5 * 6 * Authors: 7 * Dave Airlie <airlied@redhat.com> 8 * Gerd Hoffmann <kraxel@redhat.com> 9 * 10 * This work is licensed under the terms of the GNU GPL, version 2. 11 * See the COPYING file in the top-level directory. 12 */ 13 14 #ifndef HW_VIRTIO_GPU_H 15 #define HW_VIRTIO_GPU_H 16 17 #include "qemu/queue.h" 18 #include "ui/qemu-pixman.h" 19 #include "ui/console.h" 20 #include "hw/virtio/virtio.h" 21 #include "qemu/log.h" 22 #include "sysemu/vhost-user-backend.h" 23 24 #include "standard-headers/linux/virtio_gpu.h" 25 #include "standard-headers/linux/virtio_ids.h" 26 #include "qom/object.h" 27 28 #define TYPE_VIRTIO_GPU_BASE "virtio-gpu-base" 29 OBJECT_DECLARE_TYPE(VirtIOGPUBase, VirtIOGPUBaseClass, 30 VIRTIO_GPU_BASE) 31 32 #define TYPE_VIRTIO_GPU "virtio-gpu-device" 33 OBJECT_DECLARE_TYPE(VirtIOGPU, VirtIOGPUClass, VIRTIO_GPU) 34 35 #define TYPE_VIRTIO_GPU_GL "virtio-gpu-gl-device" 36 OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPUGL, VIRTIO_GPU_GL) 37 38 #define TYPE_VHOST_USER_GPU "vhost-user-gpu" 39 OBJECT_DECLARE_SIMPLE_TYPE(VhostUserGPU, VHOST_USER_GPU) 40 41 struct virtio_gpu_simple_resource { 42 uint32_t resource_id; 43 uint32_t width; 44 uint32_t height; 45 uint32_t format; 46 uint64_t *addrs; 47 struct iovec *iov; 48 unsigned int iov_cnt; 49 uint32_t scanout_bitmask; 50 pixman_image_t *image; 51 uint64_t hostmem; 52 53 uint64_t blob_size; 54 void *blob; 55 int dmabuf_fd; 56 uint8_t *remapped; 57 58 QTAILQ_ENTRY(virtio_gpu_simple_resource) next; 59 }; 60 61 struct virtio_gpu_framebuffer { 62 pixman_format_code_t format; 63 uint32_t bytes_pp; 64 uint32_t width, height; 65 uint32_t stride; 66 uint32_t offset; 67 }; 68 69 struct virtio_gpu_scanout { 70 QemuConsole *con; 71 DisplaySurface *ds; 72 uint32_t width, height; 73 int x, y; 74 int invalidate; 75 uint32_t resource_id; 76 struct virtio_gpu_update_cursor cursor; 77 QEMUCursor *current_cursor; 78 }; 79 80 struct virtio_gpu_requested_state { 81 uint16_t width_mm, height_mm; 82 uint32_t width, height; 83 int x, y; 84 }; 85 86 enum virtio_gpu_base_conf_flags { 87 VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1, 88 VIRTIO_GPU_FLAG_STATS_ENABLED, 89 VIRTIO_GPU_FLAG_EDID_ENABLED, 90 VIRTIO_GPU_FLAG_DMABUF_ENABLED, 91 VIRTIO_GPU_FLAG_BLOB_ENABLED, 92 }; 93 94 #define virtio_gpu_virgl_enabled(_cfg) \ 95 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED)) 96 #define virtio_gpu_stats_enabled(_cfg) \ 97 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED)) 98 #define virtio_gpu_edid_enabled(_cfg) \ 99 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_EDID_ENABLED)) 100 #define virtio_gpu_dmabuf_enabled(_cfg) \ 101 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_DMABUF_ENABLED)) 102 #define virtio_gpu_blob_enabled(_cfg) \ 103 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_BLOB_ENABLED)) 104 105 struct virtio_gpu_base_conf { 106 uint32_t max_outputs; 107 uint32_t flags; 108 uint32_t xres; 109 uint32_t yres; 110 }; 111 112 struct virtio_gpu_ctrl_command { 113 VirtQueueElement elem; 114 VirtQueue *vq; 115 struct virtio_gpu_ctrl_hdr cmd_hdr; 116 uint32_t error; 117 bool finished; 118 QTAILQ_ENTRY(virtio_gpu_ctrl_command) next; 119 }; 120 121 struct VirtIOGPUBase { 122 VirtIODevice parent_obj; 123 124 Error *migration_blocker; 125 126 struct virtio_gpu_base_conf conf; 127 struct virtio_gpu_config virtio_config; 128 const GraphicHwOps *hw_ops; 129 130 int renderer_blocked; 131 int enable; 132 133 struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS]; 134 135 int enabled_output_bitmask; 136 struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS]; 137 }; 138 139 struct VirtIOGPUBaseClass { 140 VirtioDeviceClass parent; 141 142 void (*gl_flushed)(VirtIOGPUBase *g); 143 }; 144 145 #define VIRTIO_GPU_BASE_PROPERTIES(_state, _conf) \ 146 DEFINE_PROP_UINT32("max_outputs", _state, _conf.max_outputs, 1), \ 147 DEFINE_PROP_BIT("edid", _state, _conf.flags, \ 148 VIRTIO_GPU_FLAG_EDID_ENABLED, true), \ 149 DEFINE_PROP_UINT32("xres", _state, _conf.xres, 1280), \ 150 DEFINE_PROP_UINT32("yres", _state, _conf.yres, 800) 151 152 typedef struct VGPUDMABuf { 153 QemuDmaBuf buf; 154 uint32_t scanout_id; 155 QTAILQ_ENTRY(VGPUDMABuf) next; 156 } VGPUDMABuf; 157 158 struct VirtIOGPU { 159 VirtIOGPUBase parent_obj; 160 161 uint64_t conf_max_hostmem; 162 163 VirtQueue *ctrl_vq; 164 VirtQueue *cursor_vq; 165 166 QEMUBH *ctrl_bh; 167 QEMUBH *cursor_bh; 168 169 QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist; 170 QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq; 171 QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq; 172 173 uint64_t hostmem; 174 175 bool processing_cmdq; 176 QEMUTimer *fence_poll; 177 QEMUTimer *print_stats; 178 179 uint32_t inflight; 180 struct { 181 uint32_t max_inflight; 182 uint32_t requests; 183 uint32_t req_3d; 184 uint32_t bytes_3d; 185 } stats; 186 187 struct { 188 QTAILQ_HEAD(, VGPUDMABuf) bufs; 189 VGPUDMABuf *primary[VIRTIO_GPU_MAX_SCANOUTS]; 190 } dmabuf; 191 }; 192 193 struct VirtIOGPUClass { 194 VirtIOGPUBaseClass parent; 195 196 void (*handle_ctrl)(VirtIODevice *vdev, VirtQueue *vq); 197 void (*process_cmd)(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd); 198 void (*update_cursor_data)(VirtIOGPU *g, 199 struct virtio_gpu_scanout *s, 200 uint32_t resource_id); 201 }; 202 203 struct VirtIOGPUGL { 204 struct VirtIOGPU parent_obj; 205 206 bool renderer_inited; 207 bool renderer_reset; 208 }; 209 210 struct VhostUserGPU { 211 VirtIOGPUBase parent_obj; 212 213 VhostUserBackend *vhost; 214 int vhost_gpu_fd; /* closed by the chardev */ 215 CharBackend vhost_chr; 216 QemuDmaBuf dmabuf[VIRTIO_GPU_MAX_SCANOUTS]; 217 bool backend_blocked; 218 }; 219 220 #define VIRTIO_GPU_FILL_CMD(out) do { \ 221 size_t s; \ 222 s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \ 223 &out, sizeof(out)); \ 224 if (s != sizeof(out)) { \ 225 qemu_log_mask(LOG_GUEST_ERROR, \ 226 "%s: command size incorrect %zu vs %zu\n", \ 227 __func__, s, sizeof(out)); \ 228 return; \ 229 } \ 230 } while (0) 231 232 /* virtio-gpu-base.c */ 233 bool virtio_gpu_base_device_realize(DeviceState *qdev, 234 VirtIOHandleOutput ctrl_cb, 235 VirtIOHandleOutput cursor_cb, 236 Error **errp); 237 void virtio_gpu_base_reset(VirtIOGPUBase *g); 238 void virtio_gpu_base_fill_display_info(VirtIOGPUBase *g, 239 struct virtio_gpu_resp_display_info *dpy_info); 240 241 /* virtio-gpu.c */ 242 void virtio_gpu_ctrl_response(VirtIOGPU *g, 243 struct virtio_gpu_ctrl_command *cmd, 244 struct virtio_gpu_ctrl_hdr *resp, 245 size_t resp_len); 246 void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g, 247 struct virtio_gpu_ctrl_command *cmd, 248 enum virtio_gpu_ctrl_type type); 249 void virtio_gpu_get_display_info(VirtIOGPU *g, 250 struct virtio_gpu_ctrl_command *cmd); 251 void virtio_gpu_get_edid(VirtIOGPU *g, 252 struct virtio_gpu_ctrl_command *cmd); 253 int virtio_gpu_create_mapping_iov(VirtIOGPU *g, 254 uint32_t nr_entries, uint32_t offset, 255 struct virtio_gpu_ctrl_command *cmd, 256 uint64_t **addr, struct iovec **iov, 257 uint32_t *niov); 258 void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g, 259 struct iovec *iov, uint32_t count); 260 void virtio_gpu_process_cmdq(VirtIOGPU *g); 261 void virtio_gpu_device_realize(DeviceState *qdev, Error **errp); 262 void virtio_gpu_reset(VirtIODevice *vdev); 263 void virtio_gpu_simple_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd); 264 void virtio_gpu_update_cursor_data(VirtIOGPU *g, 265 struct virtio_gpu_scanout *s, 266 uint32_t resource_id); 267 268 /* virtio-gpu-udmabuf.c */ 269 bool virtio_gpu_have_udmabuf(void); 270 void virtio_gpu_init_udmabuf(struct virtio_gpu_simple_resource *res); 271 void virtio_gpu_fini_udmabuf(struct virtio_gpu_simple_resource *res); 272 int virtio_gpu_update_dmabuf(VirtIOGPU *g, 273 uint32_t scanout_id, 274 struct virtio_gpu_simple_resource *res, 275 struct virtio_gpu_framebuffer *fb, 276 struct virtio_gpu_rect *r); 277 278 /* virtio-gpu-3d.c */ 279 void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, 280 struct virtio_gpu_ctrl_command *cmd); 281 void virtio_gpu_virgl_fence_poll(VirtIOGPU *g); 282 void virtio_gpu_virgl_reset_scanout(VirtIOGPU *g); 283 void virtio_gpu_virgl_reset(VirtIOGPU *g); 284 int virtio_gpu_virgl_init(VirtIOGPU *g); 285 int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g); 286 287 #endif 288