1 /* 2 * Virtio GPU Device 3 * 4 * Copyright Red Hat, Inc. 2013-2014 5 * 6 * Authors: 7 * Dave Airlie <airlied@redhat.com> 8 * Gerd Hoffmann <kraxel@redhat.com> 9 * 10 * This work is licensed under the terms of the GNU GPL, version 2. 11 * See the COPYING file in the top-level directory. 12 */ 13 14 #ifndef HW_VIRTIO_GPU_H 15 #define HW_VIRTIO_GPU_H 16 17 #include "qemu/queue.h" 18 #include "ui/qemu-pixman.h" 19 #include "ui/console.h" 20 #include "hw/virtio/virtio.h" 21 #include "qemu/log.h" 22 #include "sysemu/vhost-user-backend.h" 23 24 #include "standard-headers/linux/virtio_gpu.h" 25 #include "standard-headers/linux/virtio_ids.h" 26 #include "qom/object.h" 27 28 #define TYPE_VIRTIO_GPU_BASE "virtio-gpu-base" 29 OBJECT_DECLARE_TYPE(VirtIOGPUBase, VirtIOGPUBaseClass, 30 VIRTIO_GPU_BASE) 31 32 #define TYPE_VIRTIO_GPU "virtio-gpu-device" 33 OBJECT_DECLARE_TYPE(VirtIOGPU, VirtIOGPUClass, VIRTIO_GPU) 34 35 #define TYPE_VIRTIO_GPU_GL "virtio-gpu-gl-device" 36 OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPUGL, VIRTIO_GPU_GL) 37 38 #define TYPE_VHOST_USER_GPU "vhost-user-gpu" 39 OBJECT_DECLARE_SIMPLE_TYPE(VhostUserGPU, VHOST_USER_GPU) 40 41 #define TYPE_VIRTIO_GPU_RUTABAGA "virtio-gpu-rutabaga-device" 42 OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPURutabaga, VIRTIO_GPU_RUTABAGA) 43 44 struct virtio_gpu_simple_resource { 45 uint32_t resource_id; 46 uint32_t width; 47 uint32_t height; 48 uint32_t format; 49 uint64_t *addrs; 50 struct iovec *iov; 51 unsigned int iov_cnt; 52 uint32_t scanout_bitmask; 53 pixman_image_t *image; 54 #ifdef WIN32 55 HANDLE handle; 56 #endif 57 uint64_t hostmem; 58 59 uint64_t blob_size; 60 void *blob; 61 int dmabuf_fd; 62 uint8_t *remapped; 63 64 QTAILQ_ENTRY(virtio_gpu_simple_resource) next; 65 }; 66 67 struct virtio_gpu_framebuffer { 68 pixman_format_code_t format; 69 uint32_t bytes_pp; 70 uint32_t width, height; 71 uint32_t stride; 72 uint32_t offset; 73 }; 74 75 struct virtio_gpu_scanout { 76 QemuConsole *con; 77 DisplaySurface *ds; 78 uint32_t width, height; 79 int x, y; 80 int invalidate; 81 uint32_t resource_id; 82 struct virtio_gpu_update_cursor cursor; 83 QEMUCursor *current_cursor; 84 }; 85 86 struct virtio_gpu_requested_state { 87 uint16_t width_mm, height_mm; 88 uint32_t width, height; 89 uint32_t refresh_rate; 90 int x, y; 91 }; 92 93 enum virtio_gpu_base_conf_flags { 94 VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1, 95 VIRTIO_GPU_FLAG_STATS_ENABLED, 96 VIRTIO_GPU_FLAG_EDID_ENABLED, 97 VIRTIO_GPU_FLAG_DMABUF_ENABLED, 98 VIRTIO_GPU_FLAG_BLOB_ENABLED, 99 VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED, 100 VIRTIO_GPU_FLAG_RUTABAGA_ENABLED, 101 }; 102 103 #define virtio_gpu_virgl_enabled(_cfg) \ 104 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED)) 105 #define virtio_gpu_stats_enabled(_cfg) \ 106 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED)) 107 #define virtio_gpu_edid_enabled(_cfg) \ 108 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_EDID_ENABLED)) 109 #define virtio_gpu_dmabuf_enabled(_cfg) \ 110 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_DMABUF_ENABLED)) 111 #define virtio_gpu_blob_enabled(_cfg) \ 112 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_BLOB_ENABLED)) 113 #define virtio_gpu_context_init_enabled(_cfg) \ 114 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED)) 115 #define virtio_gpu_rutabaga_enabled(_cfg) \ 116 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_RUTABAGA_ENABLED)) 117 #define virtio_gpu_hostmem_enabled(_cfg) \ 118 (_cfg.hostmem > 0) 119 120 struct virtio_gpu_base_conf { 121 uint32_t max_outputs; 122 uint32_t flags; 123 uint32_t xres; 124 uint32_t yres; 125 uint64_t hostmem; 126 }; 127 128 struct virtio_gpu_ctrl_command { 129 VirtQueueElement elem; 130 VirtQueue *vq; 131 struct virtio_gpu_ctrl_hdr cmd_hdr; 132 uint32_t error; 133 bool finished; 134 QTAILQ_ENTRY(virtio_gpu_ctrl_command) next; 135 }; 136 137 struct VirtIOGPUBase { 138 VirtIODevice parent_obj; 139 140 Error *migration_blocker; 141 142 struct virtio_gpu_base_conf conf; 143 struct virtio_gpu_config virtio_config; 144 const GraphicHwOps *hw_ops; 145 146 int renderer_blocked; 147 int enable; 148 149 MemoryRegion hostmem; 150 151 struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS]; 152 153 int enabled_output_bitmask; 154 struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS]; 155 }; 156 157 struct VirtIOGPUBaseClass { 158 VirtioDeviceClass parent; 159 160 void (*gl_flushed)(VirtIOGPUBase *g); 161 }; 162 163 #define VIRTIO_GPU_BASE_PROPERTIES(_state, _conf) \ 164 DEFINE_PROP_UINT32("max_outputs", _state, _conf.max_outputs, 1), \ 165 DEFINE_PROP_BIT("edid", _state, _conf.flags, \ 166 VIRTIO_GPU_FLAG_EDID_ENABLED, true), \ 167 DEFINE_PROP_UINT32("xres", _state, _conf.xres, 1280), \ 168 DEFINE_PROP_UINT32("yres", _state, _conf.yres, 800) 169 170 typedef struct VGPUDMABuf { 171 QemuDmaBuf buf; 172 uint32_t scanout_id; 173 QTAILQ_ENTRY(VGPUDMABuf) next; 174 } VGPUDMABuf; 175 176 struct VirtIOGPU { 177 VirtIOGPUBase parent_obj; 178 179 uint64_t conf_max_hostmem; 180 181 VirtQueue *ctrl_vq; 182 VirtQueue *cursor_vq; 183 184 QEMUBH *ctrl_bh; 185 QEMUBH *cursor_bh; 186 QEMUBH *reset_bh; 187 QemuCond reset_cond; 188 bool reset_finished; 189 190 QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist; 191 QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq; 192 QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq; 193 194 uint64_t hostmem; 195 196 bool processing_cmdq; 197 QEMUTimer *fence_poll; 198 QEMUTimer *print_stats; 199 200 uint32_t inflight; 201 struct { 202 uint32_t max_inflight; 203 uint32_t requests; 204 uint32_t req_3d; 205 uint32_t bytes_3d; 206 } stats; 207 208 struct { 209 QTAILQ_HEAD(, VGPUDMABuf) bufs; 210 VGPUDMABuf *primary[VIRTIO_GPU_MAX_SCANOUTS]; 211 } dmabuf; 212 }; 213 214 struct VirtIOGPUClass { 215 VirtIOGPUBaseClass parent; 216 217 void (*handle_ctrl)(VirtIODevice *vdev, VirtQueue *vq); 218 void (*process_cmd)(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd); 219 void (*update_cursor_data)(VirtIOGPU *g, 220 struct virtio_gpu_scanout *s, 221 uint32_t resource_id); 222 void (*resource_destroy)(VirtIOGPU *g, 223 struct virtio_gpu_simple_resource *res, 224 Error **errp); 225 }; 226 227 struct VirtIOGPUGL { 228 struct VirtIOGPU parent_obj; 229 230 bool renderer_inited; 231 bool renderer_reset; 232 }; 233 234 struct VhostUserGPU { 235 VirtIOGPUBase parent_obj; 236 237 VhostUserBackend *vhost; 238 int vhost_gpu_fd; /* closed by the chardev */ 239 CharBackend vhost_chr; 240 QemuDmaBuf dmabuf[VIRTIO_GPU_MAX_SCANOUTS]; 241 bool backend_blocked; 242 }; 243 244 #define MAX_SLOTS 4096 245 246 struct MemoryRegionInfo { 247 int used; 248 MemoryRegion mr; 249 uint32_t resource_id; 250 }; 251 252 struct rutabaga; 253 254 struct VirtIOGPURutabaga { 255 VirtIOGPU parent_obj; 256 struct MemoryRegionInfo memory_regions[MAX_SLOTS]; 257 uint64_t capset_mask; 258 char *wayland_socket_path; 259 char *wsi; 260 bool headless; 261 uint32_t num_capsets; 262 struct rutabaga *rutabaga; 263 }; 264 265 #define VIRTIO_GPU_FILL_CMD(out) do { \ 266 size_t virtiogpufillcmd_s_ = \ 267 iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \ 268 &out, sizeof(out)); \ 269 if (virtiogpufillcmd_s_ != sizeof(out)) { \ 270 qemu_log_mask(LOG_GUEST_ERROR, \ 271 "%s: command size incorrect %zu vs %zu\n", \ 272 __func__, virtiogpufillcmd_s_, sizeof(out)); \ 273 return; \ 274 } \ 275 } while (0) 276 277 /* virtio-gpu-base.c */ 278 bool virtio_gpu_base_device_realize(DeviceState *qdev, 279 VirtIOHandleOutput ctrl_cb, 280 VirtIOHandleOutput cursor_cb, 281 Error **errp); 282 void virtio_gpu_base_device_unrealize(DeviceState *qdev); 283 void virtio_gpu_base_reset(VirtIOGPUBase *g); 284 void virtio_gpu_base_fill_display_info(VirtIOGPUBase *g, 285 struct virtio_gpu_resp_display_info *dpy_info); 286 287 void virtio_gpu_base_generate_edid(VirtIOGPUBase *g, int scanout, 288 struct virtio_gpu_resp_edid *edid); 289 /* virtio-gpu.c */ 290 struct virtio_gpu_simple_resource * 291 virtio_gpu_find_resource(VirtIOGPU *g, uint32_t resource_id); 292 293 void virtio_gpu_ctrl_response(VirtIOGPU *g, 294 struct virtio_gpu_ctrl_command *cmd, 295 struct virtio_gpu_ctrl_hdr *resp, 296 size_t resp_len); 297 void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g, 298 struct virtio_gpu_ctrl_command *cmd, 299 enum virtio_gpu_ctrl_type type); 300 void virtio_gpu_get_display_info(VirtIOGPU *g, 301 struct virtio_gpu_ctrl_command *cmd); 302 void virtio_gpu_get_edid(VirtIOGPU *g, 303 struct virtio_gpu_ctrl_command *cmd); 304 int virtio_gpu_create_mapping_iov(VirtIOGPU *g, 305 uint32_t nr_entries, uint32_t offset, 306 struct virtio_gpu_ctrl_command *cmd, 307 uint64_t **addr, struct iovec **iov, 308 uint32_t *niov); 309 void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g, 310 struct iovec *iov, uint32_t count); 311 void virtio_gpu_cleanup_mapping(VirtIOGPU *g, 312 struct virtio_gpu_simple_resource *res); 313 void virtio_gpu_process_cmdq(VirtIOGPU *g); 314 void virtio_gpu_device_realize(DeviceState *qdev, Error **errp); 315 void virtio_gpu_reset(VirtIODevice *vdev); 316 void virtio_gpu_simple_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd); 317 void virtio_gpu_update_cursor_data(VirtIOGPU *g, 318 struct virtio_gpu_scanout *s, 319 uint32_t resource_id); 320 321 /* virtio-gpu-udmabuf.c */ 322 bool virtio_gpu_have_udmabuf(void); 323 void virtio_gpu_init_udmabuf(struct virtio_gpu_simple_resource *res); 324 void virtio_gpu_fini_udmabuf(struct virtio_gpu_simple_resource *res); 325 int virtio_gpu_update_dmabuf(VirtIOGPU *g, 326 uint32_t scanout_id, 327 struct virtio_gpu_simple_resource *res, 328 struct virtio_gpu_framebuffer *fb, 329 struct virtio_gpu_rect *r); 330 331 /* virtio-gpu-3d.c */ 332 void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, 333 struct virtio_gpu_ctrl_command *cmd); 334 void virtio_gpu_virgl_fence_poll(VirtIOGPU *g); 335 void virtio_gpu_virgl_reset_scanout(VirtIOGPU *g); 336 void virtio_gpu_virgl_reset(VirtIOGPU *g); 337 int virtio_gpu_virgl_init(VirtIOGPU *g); 338 int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g); 339 340 #endif 341