xref: /openbmc/qemu/include/hw/timer/npcm7xx_timer.h (revision fca9d723)
1 /*
2  * Nuvoton NPCM7xx Timer Controller
3  *
4  * Copyright 2020 Google LLC
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License as published by the
8  * Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14  * for more details.
15  */
16 #ifndef NPCM7XX_TIMER_H
17 #define NPCM7XX_TIMER_H
18 
19 #include "exec/memory.h"
20 #include "hw/sysbus.h"
21 #include "qemu/timer.h"
22 
23 /* Each Timer Module (TIM) instance holds five 25 MHz timers. */
24 #define NPCM7XX_TIMERS_PER_CTRL (5)
25 
26 /*
27  * Number of registers in our device state structure. Don't change this without
28  * incrementing the version_id in the vmstate.
29  */
30 #define NPCM7XX_TIMER_NR_REGS (0x54 / sizeof(uint32_t))
31 
32 typedef struct NPCM7xxTimerCtrlState NPCM7xxTimerCtrlState;
33 
34 /**
35  * struct NPCM7xxTimer - Individual timer state.
36  * @irq: GIC interrupt line to fire on expiration (if enabled).
37  * @qtimer: QEMU timer that notifies us on expiration.
38  * @expires_ns: Absolute virtual expiration time.
39  * @remaining_ns: Remaining time until expiration if timer is paused.
40  * @tcsr: The Timer Control and Status Register.
41  * @ticr: The Timer Initial Count Register.
42  */
43 typedef struct NPCM7xxTimer {
44     NPCM7xxTimerCtrlState *ctrl;
45 
46     qemu_irq    irq;
47     QEMUTimer   qtimer;
48     int64_t     expires_ns;
49     int64_t     remaining_ns;
50 
51     uint32_t    tcsr;
52     uint32_t    ticr;
53 } NPCM7xxTimer;
54 
55 /**
56  * struct NPCM7xxTimerCtrlState - Timer Module device state.
57  * @parent: System bus device.
58  * @iomem: Memory region through which registers are accessed.
59  * @tisr: The Timer Interrupt Status Register.
60  * @wtcr: The Watchdog Timer Control Register.
61  * @timer: The five individual timers managed by this module.
62  */
63 struct NPCM7xxTimerCtrlState {
64     SysBusDevice parent;
65 
66     MemoryRegion iomem;
67 
68     uint32_t    tisr;
69     uint32_t    wtcr;
70 
71     NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
72 };
73 
74 #define TYPE_NPCM7XX_TIMER "npcm7xx-timer"
75 #define NPCM7XX_TIMER(obj)                                              \
76     OBJECT_CHECK(NPCM7xxTimerCtrlState, (obj), TYPE_NPCM7XX_TIMER)
77 
78 #endif /* NPCM7XX_TIMER_H */
79