xref: /openbmc/qemu/include/hw/timer/aspeed_timer.h (revision 6016b7b4)
1 /*
2  *  ASPEED AST2400 Timer
3  *
4  *  Andrew Jeffery <andrew@aj.id.au>
5  *
6  *  Copyright (C) 2016 IBM Corp.
7  *
8  *  This program is free software; you can redistribute it and/or modify
9  *  it under the terms of the GNU General Public License as published by
10  *  the Free Software Foundation; either version 2 of the License, or
11  *  (at your option) any later version.
12  *
13  *  This program is distributed in the hope that it will be useful,
14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *  GNU General Public License for more details.
17  *
18  *  You should have received a copy of the GNU General Public License along
19  *  with this program; if not, write to the Free Software Foundation, Inc.,
20  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21  */
22 #ifndef ASPEED_TIMER_H
23 #define ASPEED_TIMER_H
24 
25 #include "qemu/timer.h"
26 #include "hw/misc/aspeed_scu.h"
27 #include "qom/object.h"
28 
29 #define TYPE_ASPEED_TIMER "aspeed.timer"
30 OBJECT_DECLARE_TYPE(AspeedTimerCtrlState, AspeedTimerClass, ASPEED_TIMER)
31 #define TYPE_ASPEED_2400_TIMER TYPE_ASPEED_TIMER "-ast2400"
32 #define TYPE_ASPEED_2500_TIMER TYPE_ASPEED_TIMER "-ast2500"
33 #define TYPE_ASPEED_2600_TIMER TYPE_ASPEED_TIMER "-ast2600"
34 
35 #define ASPEED_TIMER_NR_TIMERS 8
36 
37 typedef struct AspeedTimer {
38     qemu_irq irq;
39 
40     uint8_t id;
41     QEMUTimer timer;
42 
43     /**
44      * Track the line level as the ASPEED timers implement edge triggered
45      * interrupts, signalling with both the rising and falling edge.
46      */
47     int32_t level;
48     uint32_t reload;
49     uint32_t match[2];
50     uint64_t start;
51 } AspeedTimer;
52 
53 struct AspeedTimerCtrlState {
54     /*< private >*/
55     SysBusDevice parent;
56 
57     /*< public >*/
58     MemoryRegion iomem;
59 
60     uint32_t ctrl;
61     uint32_t ctrl2;
62     uint32_t ctrl3;
63     uint32_t irq_sts;
64     AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
65 
66     AspeedSCUState *scu;
67 };
68 
69 
70 struct AspeedTimerClass {
71     SysBusDeviceClass parent_class;
72 
73     uint64_t (*read)(AspeedTimerCtrlState *s, hwaddr offset);
74     void (*write)(AspeedTimerCtrlState *s, hwaddr offset, uint64_t value);
75 };
76 
77 #endif /* ASPEED_TIMER_H */
78