1 /* 2 * Global peripheral timer block for ARM A9MP 3 * 4 * (C) 2013 Xilinx Inc. 5 * 6 * Written by François LEGAL 7 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #ifndef A9GTIMER_H 24 #define A9GTIMER_H 25 26 #include "hw/sysbus.h" 27 #include "qom/object.h" 28 29 #define A9_GTIMER_MAX_CPUS 4 30 31 #define TYPE_A9_GTIMER "arm.cortex-a9-global-timer" 32 typedef struct A9GTimerState A9GTimerState; 33 DECLARE_INSTANCE_CHECKER(A9GTimerState, A9_GTIMER, 34 TYPE_A9_GTIMER) 35 36 #define R_COUNTER_LO 0x00 37 #define R_COUNTER_HI 0x04 38 39 #define R_CONTROL 0x08 40 #define R_CONTROL_TIMER_ENABLE (1 << 0) 41 #define R_CONTROL_COMP_ENABLE (1 << 1) 42 #define R_CONTROL_IRQ_ENABLE (1 << 2) 43 #define R_CONTROL_AUTO_INCREMENT (1 << 3) 44 #define R_CONTROL_PRESCALER_SHIFT 8 45 #define R_CONTROL_PRESCALER_LEN 8 46 #define R_CONTROL_PRESCALER_MASK (((1 << R_CONTROL_PRESCALER_LEN) - 1) << \ 47 R_CONTROL_PRESCALER_SHIFT) 48 49 #define R_CONTROL_BANKED (R_CONTROL_COMP_ENABLE | \ 50 R_CONTROL_IRQ_ENABLE | \ 51 R_CONTROL_AUTO_INCREMENT) 52 #define R_CONTROL_NEEDS_SYNC (R_CONTROL_TIMER_ENABLE | \ 53 R_CONTROL_PRESCALER_MASK) 54 55 #define R_INTERRUPT_STATUS 0x0C 56 #define R_COMPARATOR_LO 0x10 57 #define R_COMPARATOR_HI 0x14 58 #define R_AUTO_INCREMENT 0x18 59 60 typedef struct A9GTimerPerCPU A9GTimerPerCPU; 61 62 struct A9GTimerPerCPU { 63 A9GTimerState *parent; 64 65 uint32_t control; /* only per cpu banked bits valid */ 66 uint64_t compare; 67 uint32_t status; 68 uint32_t inc; 69 70 MemoryRegion iomem; 71 qemu_irq irq; /* PPI interrupts */ 72 }; 73 74 struct A9GTimerState { 75 /*< private >*/ 76 SysBusDevice parent_obj; 77 /*< public >*/ 78 79 MemoryRegion iomem; 80 /* static props */ 81 uint32_t num_cpu; 82 83 QEMUTimer *timer; 84 85 uint64_t counter; /* current timer value */ 86 87 uint64_t ref_counter; 88 uint64_t cpu_ref_time; /* the cpu time as of last update of ref_counter */ 89 uint32_t control; /* only non per cpu banked bits valid */ 90 91 A9GTimerPerCPU per_cpu[A9_GTIMER_MAX_CPUS]; 92 }; 93 94 typedef struct A9GTimerUpdate { 95 uint64_t now; 96 uint64_t new; 97 } A9GTimerUpdate; 98 99 #endif /* A9GTIMER_H */ 100