1 /* 2 * Header file for the Xilinx Zynq SPI controller 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef XILINX_SPIPS_H 26 #define XILINX_SPIPS_H 27 28 #include "hw/ssi/ssi.h" 29 #include "qemu/fifo32.h" 30 #include "hw/stream.h" 31 #include "hw/sysbus.h" 32 #include "qom/object.h" 33 34 typedef struct XilinxSPIPS XilinxSPIPS; 35 36 #define XLNX_SPIPS_R_MAX (0x100 / 4) 37 #define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4) 38 39 /* Bite off 4k chunks at a time */ 40 #define LQSPI_CACHE_SIZE 1024 41 42 #define QSPI_DMA_MAX_BURST_SIZE 2048 43 44 typedef enum { 45 READ = 0x3, READ_4 = 0x13, 46 FAST_READ = 0xb, FAST_READ_4 = 0x0c, 47 DOR = 0x3b, DOR_4 = 0x3c, 48 QOR = 0x6b, QOR_4 = 0x6c, 49 DIOR = 0xbb, DIOR_4 = 0xbc, 50 QIOR = 0xeb, QIOR_4 = 0xec, 51 52 PP = 0x2, PP_4 = 0x12, 53 DPP = 0xa2, 54 QPP = 0x32, QPP_4 = 0x34, 55 } FlashCMD; 56 57 struct XilinxSPIPS { 58 SysBusDevice parent_obj; 59 60 MemoryRegion iomem; 61 MemoryRegion mmlqspi; 62 63 qemu_irq irq; 64 int irqline; 65 66 uint8_t num_cs; 67 uint8_t num_busses; 68 69 uint8_t snoop_state; 70 int cmd_dummies; 71 uint8_t link_state; 72 uint8_t link_state_next; 73 uint8_t link_state_next_when; 74 qemu_irq *cs_lines; 75 bool *cs_lines_state; 76 SSIBus **spi; 77 78 Fifo8 rx_fifo; 79 Fifo8 tx_fifo; 80 81 uint8_t num_txrx_bytes; 82 uint32_t rx_discard; 83 84 uint32_t regs[XLNX_SPIPS_R_MAX]; 85 86 bool man_start_com; 87 }; 88 89 struct XilinxQSPIPS { 90 XilinxSPIPS parent_obj; 91 92 uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; 93 hwaddr lqspi_cached_addr; 94 Error *migration_blocker; 95 bool mmio_execution_enabled; 96 }; 97 typedef struct XilinxQSPIPS XilinxQSPIPS; 98 99 struct XlnxZynqMPQSPIPS { 100 XilinxQSPIPS parent_obj; 101 102 StreamSink *dma; 103 int gqspi_irqline; 104 105 uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX]; 106 107 /* GQSPI has seperate tx/rx fifos */ 108 Fifo8 rx_fifo_g; 109 Fifo8 tx_fifo_g; 110 Fifo32 fifo_g; 111 /* 112 * At the end of each generic command, misaligned extra bytes are discard 113 * or padded to tx and rx respectively to round it out (and avoid need for 114 * individual byte access. Since we use byte fifos, keep track of the 115 * alignment WRT to word access. 116 */ 117 uint8_t rx_fifo_g_align; 118 uint8_t tx_fifo_g_align; 119 bool man_start_com_g; 120 uint32_t dma_burst_size; 121 uint8_t dma_buf[QSPI_DMA_MAX_BURST_SIZE]; 122 }; 123 124 struct XilinxSPIPSClass { 125 SysBusDeviceClass parent_class; 126 127 const MemoryRegionOps *reg_ops; 128 129 uint32_t rx_fifo_size; 130 uint32_t tx_fifo_size; 131 }; 132 133 #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" 134 #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" 135 #define TYPE_XLNX_ZYNQMP_QSPIPS "xlnx.usmp-gqspi" 136 137 OBJECT_DECLARE_TYPE(XilinxSPIPS, XilinxSPIPSClass, XILINX_SPIPS) 138 139 OBJECT_DECLARE_SIMPLE_TYPE(XilinxQSPIPS, XILINX_QSPIPS) 140 141 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPQSPIPS, XLNX_ZYNQMP_QSPIPS) 142 143 #endif /* XILINX_SPIPS_H */ 144