1 /* 2 * QEMU PowerPC SPI model 3 * 4 * Copyright (c) 2024, IBM Corporation. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 * 8 * This model Supports a connection to a single SPI responder. 9 * Introduced for P10 to provide access to SPI seeproms, TPM, flash device 10 * and an ADC controller. 11 * 12 * All SPI function control is mapped into the SPI register space to enable 13 * full control by firmware. 14 * 15 * SPI Controller has sequencer and shift engine. The SPI shift engine 16 * performs serialization and de-serialization according to the control by 17 * the sequencer and according to the setup defined in the configuration 18 * registers and the SPI sequencer implements the main control logic. 19 */ 20 21 #ifndef PPC_PNV_SPI_H 22 #define PPC_PNV_SPI_H 23 24 #include "hw/ssi/ssi.h" 25 #include "hw/sysbus.h" 26 27 #define TYPE_PNV_SPI "pnv-spi" 28 OBJECT_DECLARE_SIMPLE_TYPE(PnvSpi, PNV_SPI) 29 30 #define PNV_SPI_REG_SIZE 8 31 #define PNV_SPI_REGS 7 32 33 #define TYPE_PNV_SPI_BUS "pnv-spi-bus" 34 typedef struct PnvSpi { 35 SysBusDevice parent_obj; 36 37 SSIBus *ssi_bus; 38 qemu_irq *cs_line; 39 MemoryRegion xscom_spic_regs; 40 /* SPI object number */ 41 uint32_t spic_num; 42 uint8_t transfer_len; 43 uint8_t responder_select; 44 /* To verify if shift_n1 happens prior to shift_n2 */ 45 bool shift_n1_done; 46 /* Loop counter for branch operation opcode Ex/Fx */ 47 uint8_t loop_counter_1; 48 uint8_t loop_counter_2; 49 /* N1/N2_bits specifies the size of the N1/N2 segment of a frame in bits.*/ 50 uint8_t N1_bits; 51 uint8_t N2_bits; 52 /* Number of bytes in a payload for the N1/N2 frame segment.*/ 53 uint8_t N1_bytes; 54 uint8_t N2_bytes; 55 /* Number of N1/N2 bytes marked for transmit */ 56 uint8_t N1_tx; 57 uint8_t N2_tx; 58 /* Number of N1/N2 bytes marked for receive */ 59 uint8_t N1_rx; 60 uint8_t N2_rx; 61 62 /* SPI registers */ 63 uint64_t regs[PNV_SPI_REGS]; 64 uint8_t seq_op[PNV_SPI_REG_SIZE]; 65 uint64_t status; 66 } PnvSpi; 67 #endif /* PPC_PNV_SPI_H */ 68