1*29318db1SChalapathi V /* 2*29318db1SChalapathi V * QEMU PowerPC SPI model 3*29318db1SChalapathi V * 4*29318db1SChalapathi V * Copyright (c) 2024, IBM Corporation. 5*29318db1SChalapathi V * 6*29318db1SChalapathi V * SPDX-License-Identifier: GPL-2.0-or-later 7*29318db1SChalapathi V * 8*29318db1SChalapathi V * This model Supports a connection to a single SPI responder. 9*29318db1SChalapathi V * Introduced for P10 to provide access to SPI seeproms, TPM, flash device 10*29318db1SChalapathi V * and an ADC controller. 11*29318db1SChalapathi V */ 12*29318db1SChalapathi V 13*29318db1SChalapathi V #ifndef PPC_PNV_SPI_H 14*29318db1SChalapathi V #define PPC_PNV_SPI_H 15*29318db1SChalapathi V 16*29318db1SChalapathi V #include "hw/ssi/ssi.h" 17*29318db1SChalapathi V #include "hw/sysbus.h" 18*29318db1SChalapathi V 19*29318db1SChalapathi V #define TYPE_PNV_SPI "pnv-spi" 20*29318db1SChalapathi V OBJECT_DECLARE_SIMPLE_TYPE(PnvSpi, PNV_SPI) 21*29318db1SChalapathi V 22*29318db1SChalapathi V #define PNV_SPI_REG_SIZE 8 23*29318db1SChalapathi V #define PNV_SPI_REGS 7 24*29318db1SChalapathi V 25*29318db1SChalapathi V #define TYPE_PNV_SPI_BUS "pnv-spi-bus" 26*29318db1SChalapathi V typedef struct PnvSpi { 27*29318db1SChalapathi V SysBusDevice parent_obj; 28*29318db1SChalapathi V 29*29318db1SChalapathi V SSIBus *ssi_bus; 30*29318db1SChalapathi V qemu_irq *cs_line; 31*29318db1SChalapathi V MemoryRegion xscom_spic_regs; 32*29318db1SChalapathi V /* SPI object number */ 33*29318db1SChalapathi V uint32_t spic_num; 34*29318db1SChalapathi V 35*29318db1SChalapathi V /* SPI registers */ 36*29318db1SChalapathi V uint64_t regs[PNV_SPI_REGS]; 37*29318db1SChalapathi V uint8_t seq_op[PNV_SPI_REG_SIZE]; 38*29318db1SChalapathi V uint64_t status; 39*29318db1SChalapathi V } PnvSpi; 40*29318db1SChalapathi V #endif /* PPC_PNV_SPI_H */ 41