1 /* 2 * Nuvoton Peripheral SPI Module 3 * 4 * Copyright 2023 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 #ifndef NPCM_PSPI_H 17 #define NPCM_PSPI_H 18 19 #include "hw/ssi/ssi.h" 20 #include "hw/sysbus.h" 21 22 /* 23 * Number of registers in our device state structure. Don't change this without 24 * incrementing the version_id in the vmstate. 25 */ 26 #define NPCM_PSPI_NR_REGS 3 27 28 /** 29 * NPCMPSPIState - Device state for one Flash Interface Unit. 30 * @parent: System bus device. 31 * @mmio: Memory region for register access. 32 * @spi: The SPI bus mastered by this controller. 33 * @regs: Register contents. 34 * @irq: The interrupt request queue for this module. 35 * 36 * Each PSPI has a shared bank of registers, and controls up to four chip 37 * selects. Each chip select has a dedicated memory region which may be used to 38 * read and write the flash connected to that chip select as if it were memory. 39 */ 40 typedef struct NPCMPSPIState { 41 SysBusDevice parent; 42 43 MemoryRegion mmio; 44 45 SSIBus *spi; 46 uint16_t regs[NPCM_PSPI_NR_REGS]; 47 qemu_irq irq; 48 } NPCMPSPIState; 49 50 #define TYPE_NPCM_PSPI "npcm-pspi" 51 OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI) 52 53 #endif /* NPCM_PSPI_H */ 54