1 /* 2 * ASPEED AST2400 SMC Controller (SPI Flash Only) 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef ASPEED_SMC_H 26 #define ASPEED_SMC_H 27 28 #include "hw/ssi/ssi.h" 29 #include "hw/sysbus.h" 30 31 typedef struct AspeedSegments { 32 hwaddr addr; 33 uint32_t size; 34 } AspeedSegments; 35 36 struct AspeedSMCState; 37 typedef struct AspeedSMCController { 38 const char *name; 39 uint8_t r_conf; 40 uint8_t r_ce_ctrl; 41 uint8_t r_ctrl0; 42 uint8_t r_timings; 43 uint8_t conf_enable_w0; 44 uint8_t max_slaves; 45 const AspeedSegments *segments; 46 hwaddr flash_window_base; 47 uint32_t flash_window_size; 48 bool has_dma; 49 hwaddr dma_flash_mask; 50 hwaddr dma_dram_mask; 51 uint32_t nregs; 52 } AspeedSMCController; 53 54 typedef struct AspeedSMCFlash { 55 struct AspeedSMCState *controller; 56 57 uint8_t id; 58 uint32_t size; 59 60 MemoryRegion mmio; 61 DeviceState *flash; 62 } AspeedSMCFlash; 63 64 #define TYPE_ASPEED_SMC "aspeed.smc" 65 #define ASPEED_SMC(obj) OBJECT_CHECK(AspeedSMCState, (obj), TYPE_ASPEED_SMC) 66 #define ASPEED_SMC_CLASS(klass) \ 67 OBJECT_CLASS_CHECK(AspeedSMCClass, (klass), TYPE_ASPEED_SMC) 68 #define ASPEED_SMC_GET_CLASS(obj) \ 69 OBJECT_GET_CLASS(AspeedSMCClass, (obj), TYPE_ASPEED_SMC) 70 71 typedef struct AspeedSMCClass { 72 SysBusDevice parent_obj; 73 const AspeedSMCController *ctrl; 74 } AspeedSMCClass; 75 76 #define ASPEED_SMC_R_MAX (0x100 / 4) 77 78 typedef struct AspeedSMCState { 79 SysBusDevice parent_obj; 80 81 const AspeedSMCController *ctrl; 82 83 MemoryRegion mmio; 84 MemoryRegion mmio_flash; 85 86 qemu_irq irq; 87 int irqline; 88 89 uint32_t num_cs; 90 qemu_irq *cs_lines; 91 bool inject_failure; 92 93 SSIBus *spi; 94 95 uint32_t regs[ASPEED_SMC_R_MAX]; 96 97 /* depends on the controller type */ 98 uint8_t r_conf; 99 uint8_t r_ce_ctrl; 100 uint8_t r_ctrl0; 101 uint8_t r_timings; 102 uint8_t conf_enable_w0; 103 104 /* for DMA support */ 105 uint64_t sdram_base; 106 107 AddressSpace flash_as; 108 MemoryRegion *dram_mr; 109 AddressSpace dram_as; 110 111 AspeedSMCFlash *flashes; 112 113 uint8_t snoop_index; 114 uint8_t snoop_dummies; 115 } AspeedSMCState; 116 117 #endif /* ASPEED_SMC_H */ 118