1 /* 2 * ASPEED AST2400 SMC Controller (SPI Flash Only) 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef ASPEED_SMC_H 26 #define ASPEED_SMC_H 27 28 #include "hw/ssi/ssi.h" 29 #include "hw/sysbus.h" 30 31 typedef struct AspeedSegments { 32 hwaddr addr; 33 uint32_t size; 34 } AspeedSegments; 35 36 struct AspeedSMCState; 37 typedef struct AspeedSMCController { 38 const char *name; 39 uint8_t r_conf; 40 uint8_t r_ce_ctrl; 41 uint8_t r_ctrl0; 42 uint8_t r_timings; 43 uint8_t nregs_timings; 44 uint8_t conf_enable_w0; 45 uint8_t max_slaves; 46 const AspeedSegments *segments; 47 hwaddr flash_window_base; 48 uint32_t flash_window_size; 49 bool has_dma; 50 hwaddr dma_flash_mask; 51 hwaddr dma_dram_mask; 52 uint32_t nregs; 53 uint32_t (*segment_to_reg)(const struct AspeedSMCState *s, 54 const AspeedSegments *seg); 55 void (*reg_to_segment)(const struct AspeedSMCState *s, uint32_t reg, 56 AspeedSegments *seg); 57 } AspeedSMCController; 58 59 typedef struct AspeedSMCFlash { 60 struct AspeedSMCState *controller; 61 62 uint8_t id; 63 uint32_t size; 64 65 MemoryRegion mmio; 66 DeviceState *flash; 67 } AspeedSMCFlash; 68 69 #define TYPE_ASPEED_SMC "aspeed.smc" 70 #define ASPEED_SMC(obj) OBJECT_CHECK(AspeedSMCState, (obj), TYPE_ASPEED_SMC) 71 #define ASPEED_SMC_CLASS(klass) \ 72 OBJECT_CLASS_CHECK(AspeedSMCClass, (klass), TYPE_ASPEED_SMC) 73 #define ASPEED_SMC_GET_CLASS(obj) \ 74 OBJECT_GET_CLASS(AspeedSMCClass, (obj), TYPE_ASPEED_SMC) 75 76 typedef struct AspeedSMCClass { 77 SysBusDevice parent_obj; 78 const AspeedSMCController *ctrl; 79 } AspeedSMCClass; 80 81 #define ASPEED_SMC_R_MAX (0x100 / 4) 82 83 typedef struct AspeedSMCState { 84 SysBusDevice parent_obj; 85 86 const AspeedSMCController *ctrl; 87 88 MemoryRegion mmio; 89 MemoryRegion mmio_flash; 90 91 qemu_irq irq; 92 int irqline; 93 94 uint32_t num_cs; 95 qemu_irq *cs_lines; 96 bool inject_failure; 97 98 SSIBus *spi; 99 100 uint32_t regs[ASPEED_SMC_R_MAX]; 101 102 /* depends on the controller type */ 103 uint8_t r_conf; 104 uint8_t r_ce_ctrl; 105 uint8_t r_ctrl0; 106 uint8_t r_timings; 107 uint8_t conf_enable_w0; 108 109 /* for DMA support */ 110 uint64_t sdram_base; 111 112 AddressSpace flash_as; 113 MemoryRegion *dram_mr; 114 AddressSpace dram_as; 115 116 AspeedSMCFlash *flashes; 117 118 uint8_t snoop_index; 119 uint8_t snoop_dummies; 120 } AspeedSMCState; 121 122 #endif /* ASPEED_SMC_H */ 123