1 /* 2 * ASPEED AST2400 SMC Controller (SPI Flash Only) 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef ASPEED_SMC_H 26 #define ASPEED_SMC_H 27 28 #include "hw/ssi/ssi.h" 29 #include "hw/sysbus.h" 30 #include "qom/object.h" 31 32 struct AspeedSMCState; 33 typedef struct AspeedSMCFlash { 34 struct AspeedSMCState *controller; 35 36 uint8_t id; 37 38 MemoryRegion mmio; 39 } AspeedSMCFlash; 40 41 #define TYPE_ASPEED_SMC "aspeed.smc" 42 OBJECT_DECLARE_TYPE(AspeedSMCState, AspeedSMCClass, ASPEED_SMC) 43 44 #define ASPEED_SMC_R_MAX (0x100 / 4) 45 46 struct AspeedSMCState { 47 SysBusDevice parent_obj; 48 49 MemoryRegion mmio; 50 MemoryRegion mmio_flash; 51 MemoryRegion mmio_flash_alias; 52 53 qemu_irq irq; 54 int irqline; 55 56 uint32_t num_cs; 57 qemu_irq *cs_lines; 58 bool inject_failure; 59 60 SSIBus *spi; 61 62 uint32_t regs[ASPEED_SMC_R_MAX]; 63 64 /* depends on the controller type */ 65 uint8_t r_conf; 66 uint8_t r_ce_ctrl; 67 uint8_t r_ctrl0; 68 uint8_t r_timings; 69 uint8_t conf_enable_w0; 70 71 AddressSpace flash_as; 72 MemoryRegion *dram_mr; 73 AddressSpace dram_as; 74 75 AspeedSMCFlash *flashes; 76 77 uint8_t snoop_index; 78 uint8_t snoop_dummies; 79 }; 80 81 typedef struct AspeedSegments { 82 hwaddr addr; 83 uint32_t size; 84 } AspeedSegments; 85 86 struct AspeedSMCClass { 87 SysBusDeviceClass parent_obj; 88 89 uint8_t r_conf; 90 uint8_t r_ce_ctrl; 91 uint8_t r_ctrl0; 92 uint8_t r_timings; 93 uint8_t nregs_timings; 94 uint8_t conf_enable_w0; 95 uint8_t max_peripherals; 96 const AspeedSegments *segments; 97 hwaddr flash_window_base; 98 uint32_t flash_window_size; 99 uint32_t features; 100 hwaddr dma_flash_mask; 101 hwaddr dma_dram_mask; 102 uint32_t nregs; 103 uint32_t (*segment_to_reg)(const AspeedSMCState *s, 104 const AspeedSegments *seg); 105 void (*reg_to_segment)(const AspeedSMCState *s, uint32_t reg, 106 AspeedSegments *seg); 107 void (*dma_ctrl)(AspeedSMCState *s, uint32_t value); 108 }; 109 110 #endif /* ASPEED_SMC_H */ 111