1 /* 2 * ASPEED AST2400 SMC Controller (SPI Flash Only) 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef ASPEED_SMC_H 26 #define ASPEED_SMC_H 27 28 #include "hw/ssi/ssi.h" 29 #include "hw/sysbus.h" 30 #include "qom/object.h" 31 32 struct AspeedSMCState; 33 typedef struct AspeedSMCFlash { 34 struct AspeedSMCState *controller; 35 36 uint8_t id; 37 uint32_t size; 38 39 MemoryRegion mmio; 40 DeviceState *flash; 41 } AspeedSMCFlash; 42 43 #define TYPE_ASPEED_SMC "aspeed.smc" 44 OBJECT_DECLARE_TYPE(AspeedSMCState, AspeedSMCClass, ASPEED_SMC) 45 46 #define ASPEED_SMC_R_MAX (0x100 / 4) 47 48 struct AspeedSMCState { 49 SysBusDevice parent_obj; 50 51 MemoryRegion mmio; 52 MemoryRegion mmio_flash; 53 MemoryRegion mmio_flash_alias; 54 55 qemu_irq irq; 56 int irqline; 57 58 uint32_t num_cs; 59 qemu_irq *cs_lines; 60 bool inject_failure; 61 62 SSIBus *spi; 63 64 uint32_t regs[ASPEED_SMC_R_MAX]; 65 66 /* depends on the controller type */ 67 uint8_t r_conf; 68 uint8_t r_ce_ctrl; 69 uint8_t r_ctrl0; 70 uint8_t r_timings; 71 uint8_t conf_enable_w0; 72 73 AddressSpace flash_as; 74 MemoryRegion *dram_mr; 75 AddressSpace dram_as; 76 77 AspeedSMCFlash *flashes; 78 79 uint8_t snoop_index; 80 uint8_t snoop_dummies; 81 }; 82 83 typedef struct AspeedSegments { 84 hwaddr addr; 85 uint32_t size; 86 } AspeedSegments; 87 88 struct AspeedSMCClass { 89 SysBusDeviceClass parent_obj; 90 91 uint8_t r_conf; 92 uint8_t r_ce_ctrl; 93 uint8_t r_ctrl0; 94 uint8_t r_timings; 95 uint8_t nregs_timings; 96 uint8_t conf_enable_w0; 97 uint8_t max_peripherals; 98 const AspeedSegments *segments; 99 hwaddr flash_window_base; 100 uint32_t flash_window_size; 101 uint32_t features; 102 hwaddr dma_flash_mask; 103 hwaddr dma_dram_mask; 104 uint32_t nregs; 105 uint32_t (*segment_to_reg)(const AspeedSMCState *s, 106 const AspeedSegments *seg); 107 void (*reg_to_segment)(const AspeedSMCState *s, uint32_t reg, 108 AspeedSegments *seg); 109 void (*dma_ctrl)(AspeedSMCState *s, uint32_t value); 110 }; 111 112 #endif /* ASPEED_SMC_H */ 113