1 /* 2 * ASPEED AST2400 SMC Controller (SPI Flash Only) 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef ASPEED_SMC_H 26 #define ASPEED_SMC_H 27 28 #include "hw/ssi/ssi.h" 29 #include "hw/sysbus.h" 30 31 typedef struct AspeedSegments { 32 hwaddr addr; 33 uint32_t size; 34 } AspeedSegments; 35 36 struct AspeedSMCState; 37 typedef struct AspeedSMCController { 38 const char *name; 39 uint8_t r_conf; 40 uint8_t r_ce_ctrl; 41 uint8_t r_ctrl0; 42 uint8_t r_timings; 43 uint8_t conf_enable_w0; 44 uint8_t max_slaves; 45 const AspeedSegments *segments; 46 hwaddr flash_window_base; 47 uint32_t flash_window_size; 48 bool has_dma; 49 uint32_t nregs; 50 } AspeedSMCController; 51 52 typedef struct AspeedSMCFlash { 53 struct AspeedSMCState *controller; 54 55 uint8_t id; 56 uint32_t size; 57 58 MemoryRegion mmio; 59 DeviceState *flash; 60 } AspeedSMCFlash; 61 62 #define TYPE_ASPEED_SMC "aspeed.smc" 63 #define ASPEED_SMC(obj) OBJECT_CHECK(AspeedSMCState, (obj), TYPE_ASPEED_SMC) 64 #define ASPEED_SMC_CLASS(klass) \ 65 OBJECT_CLASS_CHECK(AspeedSMCClass, (klass), TYPE_ASPEED_SMC) 66 #define ASPEED_SMC_GET_CLASS(obj) \ 67 OBJECT_GET_CLASS(AspeedSMCClass, (obj), TYPE_ASPEED_SMC) 68 69 typedef struct AspeedSMCClass { 70 SysBusDevice parent_obj; 71 const AspeedSMCController *ctrl; 72 } AspeedSMCClass; 73 74 #define ASPEED_SMC_R_MAX (0x100 / 4) 75 76 typedef struct AspeedSMCState { 77 SysBusDevice parent_obj; 78 79 const AspeedSMCController *ctrl; 80 81 MemoryRegion mmio; 82 MemoryRegion mmio_flash; 83 84 qemu_irq irq; 85 int irqline; 86 87 uint32_t num_cs; 88 qemu_irq *cs_lines; 89 90 SSIBus *spi; 91 92 uint32_t regs[ASPEED_SMC_R_MAX]; 93 94 /* depends on the controller type */ 95 uint8_t r_conf; 96 uint8_t r_ce_ctrl; 97 uint8_t r_ctrl0; 98 uint8_t r_timings; 99 uint8_t conf_enable_w0; 100 101 /* for DMA support */ 102 uint64_t sdram_base; 103 104 AspeedSMCFlash *flashes; 105 106 uint8_t snoop_index; 107 uint8_t snoop_dummies; 108 } AspeedSMCState; 109 110 #endif /* ASPEED_SMC_H */ 111