1 /* 2 * QEMU PIIX South Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2018 Hervé Poussineau 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or later. 8 * See the COPYING file in the top-level directory. 9 * 10 */ 11 12 #ifndef HW_SOUTHBRIDGE_PIIX_H 13 #define HW_SOUTHBRIDGE_PIIX_H 14 15 #include "hw/pci/pci_device.h" 16 17 /* PIRQRC[A:D]: PIRQx Route Control Registers */ 18 #define PIIX_PIRQCA 0x60 19 #define PIIX_PIRQCB 0x61 20 #define PIIX_PIRQCC 0x62 21 #define PIIX_PIRQCD 0x63 22 23 /* 24 * Reset Control Register: PCI-accessible ISA-Compatible Register at address 25 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). 26 */ 27 #define PIIX_RCR_IOPORT 0xcf9 28 29 #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ 30 #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ 31 32 struct PIIXState { 33 PCIDevice dev; 34 35 /* 36 * bitmap to track pic levels. 37 * The pic level is the logical OR of all the PCI irqs mapped to it 38 * So one PIC level is tracked by PIIX_NUM_PIRQS bits. 39 * 40 * PIRQ is mapped to PIC pins, we track it by 41 * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with 42 * pic_irq * PIIX_NUM_PIRQS + pirq 43 */ 44 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 45 #error "unable to encode pic state in 64bit in pic_levels." 46 #endif 47 uint64_t pic_levels; 48 49 qemu_irq *pic; 50 51 /* This member isn't used. Just for save/load compatibility */ 52 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; 53 54 /* Reset Control Register contents */ 55 uint8_t rcr; 56 57 /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ 58 MemoryRegion rcr_mem; 59 }; 60 typedef struct PIIXState PIIX3State; 61 62 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3" 63 DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, 64 TYPE_PIIX3_PCI_DEVICE) 65 66 #define TYPE_PIIX3_DEVICE "PIIX3" 67 #define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen" 68 #define TYPE_PIIX4_PCI_DEVICE "piix4-isa" 69 70 #endif 71