1 /* 2 * QEMU PIIX South Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2018 Hervé Poussineau 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or later. 8 * See the COPYING file in the top-level directory. 9 * 10 */ 11 12 #ifndef HW_SOUTHBRIDGE_PIIX_H 13 #define HW_SOUTHBRIDGE_PIIX_H 14 15 #include "hw/pci/pci.h" 16 17 #define TYPE_PIIX4_PM "PIIX4_PM" 18 19 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 20 qemu_irq sci_irq, qemu_irq smi_irq, 21 int smm_enabled, DeviceState **piix4_pm); 22 23 /* PIRQRC[A:D]: PIRQx Route Control Registers */ 24 #define PIIX_PIRQCA 0x60 25 #define PIIX_PIRQCB 0x61 26 #define PIIX_PIRQCC 0x62 27 #define PIIX_PIRQCD 0x63 28 29 /* 30 * Reset Control Register: PCI-accessible ISA-Compatible Register at address 31 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). 32 */ 33 #define PIIX_RCR_IOPORT 0xcf9 34 35 #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ 36 #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ 37 38 typedef struct PIIXState { 39 PCIDevice dev; 40 41 /* 42 * bitmap to track pic levels. 43 * The pic level is the logical OR of all the PCI irqs mapped to it 44 * So one PIC level is tracked by PIIX_NUM_PIRQS bits. 45 * 46 * PIRQ is mapped to PIC pins, we track it by 47 * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with 48 * pic_irq * PIIX_NUM_PIRQS + pirq 49 */ 50 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 51 #error "unable to encode pic state in 64bit in pic_levels." 52 #endif 53 uint64_t pic_levels; 54 55 qemu_irq *pic; 56 57 /* This member isn't used. Just for save/load compatibility */ 58 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; 59 60 /* Reset Control Register contents */ 61 uint8_t rcr; 62 63 /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ 64 MemoryRegion rcr_mem; 65 } PIIX3State; 66 67 extern PCIDevice *piix4_dev; 68 69 PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus); 70 71 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, 72 I2CBus **smbus, size_t ide_buses); 73 74 #endif 75