1 /* 2 * QEMU PIIX South Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2018 Hervé Poussineau 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or later. 8 * See the COPYING file in the top-level directory. 9 * 10 */ 11 12 #ifndef HW_SOUTHBRIDGE_PIIX_H 13 #define HW_SOUTHBRIDGE_PIIX_H 14 15 #include "hw/pci/pci.h" 16 #include "qom/object.h" 17 18 #define TYPE_PIIX4_PM "PIIX4_PM" 19 20 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 21 qemu_irq sci_irq, qemu_irq smi_irq, 22 int smm_enabled, DeviceState **piix4_pm); 23 24 /* PIRQRC[A:D]: PIRQx Route Control Registers */ 25 #define PIIX_PIRQCA 0x60 26 #define PIIX_PIRQCB 0x61 27 #define PIIX_PIRQCC 0x62 28 #define PIIX_PIRQCD 0x63 29 30 /* 31 * Reset Control Register: PCI-accessible ISA-Compatible Register at address 32 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). 33 */ 34 #define PIIX_RCR_IOPORT 0xcf9 35 36 #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ 37 #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ 38 39 struct PIIXState { 40 PCIDevice dev; 41 42 /* 43 * bitmap to track pic levels. 44 * The pic level is the logical OR of all the PCI irqs mapped to it 45 * So one PIC level is tracked by PIIX_NUM_PIRQS bits. 46 * 47 * PIRQ is mapped to PIC pins, we track it by 48 * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with 49 * pic_irq * PIIX_NUM_PIRQS + pirq 50 */ 51 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 52 #error "unable to encode pic state in 64bit in pic_levels." 53 #endif 54 uint64_t pic_levels; 55 56 qemu_irq *pic; 57 58 /* This member isn't used. Just for save/load compatibility */ 59 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; 60 61 /* Reset Control Register contents */ 62 uint8_t rcr; 63 64 /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ 65 MemoryRegion rcr_mem; 66 }; 67 typedef struct PIIXState PIIX3State; 68 69 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3" 70 DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, 71 TYPE_PIIX3_PCI_DEVICE) 72 73 extern PCIDevice *piix4_dev; 74 75 PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus); 76 77 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus); 78 79 #endif 80