1 #ifndef HW_SOUTHBRIDGE_ICH9_H 2 #define HW_SOUTHBRIDGE_ICH9_H 3 4 #include "hw/isa/apm.h" 5 #include "hw/acpi/ich9.h" 6 #include "hw/intc/ioapic.h" 7 #include "hw/pci/pci.h" 8 #include "hw/pci/pci_device.h" 9 #include "hw/rtc/mc146818rtc.h" 10 #include "exec/memory.h" 11 #include "qemu/notify.h" 12 #include "qom/object.h" 13 14 void ich9_generate_smi(void); 15 16 #define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */ 17 18 #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC" 19 OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE) 20 21 struct ICH9LPCState { 22 /* ICH9 LPC PCI to ISA bridge */ 23 PCIDevice d; 24 25 /* (pci device, intx) -> pirq 26 * In real chipset case, the unused slots are never used 27 * as ICH9 supports only D25-D31 irq routing. 28 * On the other hand in qemu case, any slot/function can be populated 29 * via command line option. 30 * So fallback interrupt routing for any devices in any slots is necessary. 31 */ 32 uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; 33 34 MC146818RtcState rtc; 35 APMState apm; 36 ICH9LPCPMRegs pm; 37 uint32_t sci_level; /* track sci level */ 38 uint8_t sci_gsi; 39 40 /* 2.24 Pin Straps */ 41 struct { 42 bool spkr_hi; 43 } pin_strap; 44 45 /* 10.1 Chipset Configuration registers(Memory Space) 46 which is pointed by RCBA */ 47 uint8_t chip_config[ICH9_CC_SIZE]; 48 49 /* 50 * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0) 51 * 52 * register contents and IO memory region 53 */ 54 uint8_t rst_cnt; 55 MemoryRegion rst_cnt_mem; 56 57 /* SMI feature negotiation via fw_cfg */ 58 uint64_t smi_host_features; /* guest-invisible, host endian */ 59 uint8_t smi_host_features_le[8]; /* guest-visible, read-only, little 60 * endian uint64_t */ 61 uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little 62 * endian uint64_t */ 63 uint8_t smi_features_ok; /* guest-visible, read-only; selecting it 64 * triggers feature lockdown */ 65 uint64_t smi_negotiated_features; /* guest-invisible, host endian */ 66 67 MemoryRegion rcrb_mem; /* root complex register block */ 68 Notifier machine_ready; 69 70 qemu_irq gsi[IOAPIC_NUM_PINS]; 71 }; 72 73 #define ICH9_MASK(bit, ms_bit, ls_bit) \ 74 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) 75 76 /* ICH9: Chipset Configuration Registers */ 77 #define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) 78 79 #define ICH9_CC 80 #define ICH9_CC_D28IP 0x310C 81 #define ICH9_CC_D28IP_SHIFT 4 82 #define ICH9_CC_D28IP_MASK 0xf 83 #define ICH9_CC_D28IP_DEFAULT 0x00214321 84 #define ICH9_CC_D31IR 0x3140 85 #define ICH9_CC_D30IR 0x3142 86 #define ICH9_CC_D29IR 0x3144 87 #define ICH9_CC_D28IR 0x3146 88 #define ICH9_CC_D27IR 0x3148 89 #define ICH9_CC_D26IR 0x314C 90 #define ICH9_CC_D25IR 0x3150 91 #define ICH9_CC_DIR_DEFAULT 0x3210 92 #define ICH9_CC_D30IR_DEFAULT 0x0 93 #define ICH9_CC_DIR_SHIFT 4 94 #define ICH9_CC_DIR_MASK 0x7 95 #define ICH9_CC_OIC 0x31FF 96 #define ICH9_CC_OIC_AEN 0x1 97 #define ICH9_CC_GCS 0x3410 98 #define ICH9_CC_GCS_DEFAULT 0x00000020 99 #define ICH9_CC_GCS_NO_REBOOT (1 << 5) 100 101 /* D28:F[0-5] */ 102 #define ICH9_PCIE_DEV 28 103 #define ICH9_PCIE_FUNC_MAX 6 104 105 106 /* D29:F0 USB UHCI Controller #1 */ 107 #define ICH9_USB_UHCI1_DEV 29 108 #define ICH9_USB_UHCI1_FUNC 0 109 110 /* D30:F0 DMI-to-PCI bridge */ 111 #define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE" 112 #define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0 113 114 #define ICH9_D2P_BRIDGE_DEV 30 115 #define ICH9_D2P_BRIDGE_FUNC 0 116 117 #define ICH9_D2P_SECONDARY_DEFAULT (256 - 8) 118 119 #define ICH9_D2P_A2_REVISION 0x92 120 121 /* D31:F0 LPC Processor Interface */ 122 #define ICH9_RST_CNT_IOPORT 0xCF9 123 124 /* D31:F1 LPC controller */ 125 #define ICH9_A2_LPC "ICH9 A2 LPC" 126 #define ICH9_A2_LPC_SAVEVM_VERSION 0 127 128 #define ICH9_LPC_DEV 31 129 #define ICH9_LPC_FUNC 0 130 131 #define ICH9_A2_LPC_REVISION 0x2 132 #define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ 133 134 #define ICH9_LPC_PMBASE 0x40 135 #define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ICH9_MASK(32, 15, 7) 136 #define ICH9_LPC_PMBASE_RTE 0x1 137 #define ICH9_LPC_PMBASE_DEFAULT 0x1 138 139 #define ICH9_LPC_ACPI_CTRL 0x44 140 #define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80 141 #define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK ICH9_MASK(8, 2, 0) 142 #define ICH9_LPC_ACPI_CTRL_9 0x0 143 #define ICH9_LPC_ACPI_CTRL_10 0x1 144 #define ICH9_LPC_ACPI_CTRL_11 0x2 145 #define ICH9_LPC_ACPI_CTRL_20 0x4 146 #define ICH9_LPC_ACPI_CTRL_21 0x5 147 #define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0 148 149 #define ICH9_LPC_PIRQA_ROUT 0x60 150 #define ICH9_LPC_PIRQB_ROUT 0x61 151 #define ICH9_LPC_PIRQC_ROUT 0x62 152 #define ICH9_LPC_PIRQD_ROUT 0x63 153 154 #define ICH9_LPC_PIRQE_ROUT 0x68 155 #define ICH9_LPC_PIRQF_ROUT 0x69 156 #define ICH9_LPC_PIRQG_ROUT 0x6a 157 #define ICH9_LPC_PIRQH_ROUT 0x6b 158 159 #define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80 160 #define ICH9_LPC_PIRQ_ROUT_MASK ICH9_MASK(8, 3, 0) 161 #define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80 162 163 #define ICH9_LPC_GEN_PMCON_1 0xa0 164 #define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4) 165 #define ICH9_LPC_GEN_PMCON_2 0xa2 166 #define ICH9_LPC_GEN_PMCON_3 0xa4 167 #define ICH9_LPC_GEN_PMCON_LOCK 0xa6 168 169 #define ICH9_LPC_RCBA 0xf0 170 #define ICH9_LPC_RCBA_BA_MASK ICH9_MASK(32, 31, 14) 171 #define ICH9_LPC_RCBA_EN 0x1 172 #define ICH9_LPC_RCBA_DEFAULT 0x0 173 174 #define ICH9_LPC_PIC_NUM_PINS 16 175 #define ICH9_LPC_IOAPIC_NUM_PINS 24 176 177 #define ICH9_GPIO_GSI "gsi" 178 179 /* D31:F2 SATA Controller #1 */ 180 #define ICH9_SATA1_DEV 31 181 #define ICH9_SATA1_FUNC 2 182 183 /* D31:F0 power management I/O registers 184 offset from the address ICH9_LPC_PMBASE */ 185 186 /* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ 187 #define ICH9_PMIO_SIZE 128 188 #define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) 189 190 #define ICH9_PMIO_PM1_STS 0x00 191 #define ICH9_PMIO_PM1_EN 0x02 192 #define ICH9_PMIO_PM1_CNT 0x04 193 #define ICH9_PMIO_PM1_TMR 0x08 194 #define ICH9_PMIO_GPE0_STS 0x20 195 #define ICH9_PMIO_GPE0_EN 0x28 196 #define ICH9_PMIO_GPE0_LEN 16 197 #define ICH9_PMIO_SMI_EN 0x30 198 #define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) 199 #define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13) 200 #define ICH9_PMIO_SMI_STS 0x34 201 #define ICH9_PMIO_TCO_RLD 0x60 202 #define ICH9_PMIO_TCO_LEN 32 203 204 /* FADT ACPI_ENABLE/ACPI_DISABLE */ 205 #define ICH9_APM_ACPI_ENABLE 0x2 206 #define ICH9_APM_ACPI_DISABLE 0x3 207 208 209 /* D31:F3 SMBus controller */ 210 #define TYPE_ICH9_SMB_DEVICE "ICH9-SMB" 211 212 #define ICH9_A2_SMB_REVISION 0x02 213 #define ICH9_SMB_PI 0x00 214 215 #define ICH9_SMB_SMBMBAR0 0x10 216 #define ICH9_SMB_SMBMBAR1 0x14 217 #define ICH9_SMB_SMBM_BAR 0 218 #define ICH9_SMB_SMBM_SIZE (1 << 8) 219 #define ICH9_SMB_SMB_BASE 0x20 220 #define ICH9_SMB_SMB_BASE_BAR 4 221 #define ICH9_SMB_SMB_BASE_SIZE (1 << 5) 222 #define ICH9_SMB_HOSTC 0x40 223 #define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) 224 #define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) 225 #define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) 226 #define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) 227 228 /* D31:F3 SMBus I/O and memory mapped I/O registers */ 229 #define ICH9_SMB_DEV 31 230 #define ICH9_SMB_FUNC 3 231 232 #define ICH9_SMB_HST_STS 0x00 233 #define ICH9_SMB_HST_CNT 0x02 234 #define ICH9_SMB_HST_CMD 0x03 235 #define ICH9_SMB_XMIT_SLVA 0x04 236 #define ICH9_SMB_HST_D0 0x05 237 #define ICH9_SMB_HST_D1 0x06 238 #define ICH9_SMB_HOST_BLOCK_DB 0x07 239 240 #define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features" 241 242 /* bit positions used in fw_cfg SMI feature negotiation */ 243 #define ICH9_LPC_SMI_F_BROADCAST_BIT 0 244 #define ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT 1 245 #define ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT 2 246 247 #endif /* HW_SOUTHBRIDGE_ICH9_H */ 248