1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Mitsyanko Igor <i.mitsyanko@samsung.com> 6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 7 * 8 * Based on MMC controller for Samsung S5PC1xx-based board emulation 9 * by Alexey Merkulov and Vladimir Monakhov. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU _General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #ifndef SDHCI_H 26 #define SDHCI_H 27 28 #include "hw/pci/pci.h" 29 #include "hw/sysbus.h" 30 #include "hw/sd/sd.h" 31 #include "qom/object.h" 32 33 /* SD/MMC host controller state */ 34 struct SDHCIState { 35 /*< private >*/ 36 union { 37 PCIDevice pcidev; 38 SysBusDevice busdev; 39 }; 40 41 /*< public >*/ 42 SDBus sdbus; 43 MemoryRegion iomem; 44 AddressSpace sysbus_dma_as; 45 AddressSpace *dma_as; 46 MemoryRegion *dma_mr; 47 const MemoryRegionOps *io_ops; 48 49 QEMUTimer *insert_timer; /* timer for 'changing' sd card. */ 50 QEMUTimer *transfer_timer; 51 qemu_irq irq; 52 53 /* Registers cleared on reset */ 54 uint32_t sdmasysad; /* SDMA System Address register */ 55 uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */ 56 uint16_t blkcnt; /* Blocks count for current transfer */ 57 uint32_t argument; /* Command Argument Register */ 58 uint16_t trnmod; /* Transfer Mode Setting Register */ 59 uint16_t cmdreg; /* Command Register */ 60 uint32_t rspreg[4]; /* Response Registers 0-3 */ 61 uint32_t prnsts; /* Present State Register */ 62 uint8_t hostctl1; /* Host Control Register */ 63 uint8_t pwrcon; /* Power control Register */ 64 uint8_t blkgap; /* Block Gap Control Register */ 65 uint8_t wakcon; /* WakeUp Control Register */ 66 uint16_t clkcon; /* Clock control Register */ 67 uint8_t timeoutcon; /* Timeout Control Register */ 68 uint8_t admaerr; /* ADMA Error Status Register */ 69 uint16_t norintsts; /* Normal Interrupt Status Register */ 70 uint16_t errintsts; /* Error Interrupt Status Register */ 71 uint16_t norintstsen; /* Normal Interrupt Status Enable Register */ 72 uint16_t errintstsen; /* Error Interrupt Status Enable Register */ 73 uint16_t norintsigen; /* Normal Interrupt Signal Enable Register */ 74 uint16_t errintsigen; /* Error Interrupt Signal Enable Register */ 75 uint16_t acmd12errsts; /* Auto CMD12 error status register */ 76 uint16_t hostctl2; /* Host Control 2 */ 77 uint64_t admasysaddr; /* ADMA System Address Register */ 78 uint16_t vendor_spec; /* Vendor specific register */ 79 80 /* Read-only registers */ 81 uint64_t capareg; /* Capabilities Register */ 82 uint64_t maxcurr; /* Maximum Current Capabilities Register */ 83 uint16_t version; /* Host Controller Version Register */ 84 85 uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */ 86 uint32_t buf_maxsz; 87 uint16_t data_count; /* current element in FIFO buffer */ 88 uint8_t stopped_state;/* Current SDHC state */ 89 bool pending_insert_state; 90 /* Buffer Data Port Register - virtual access point to R and W buffers */ 91 /* Software Reset Register - always reads as 0 */ 92 /* Force Event Auto CMD12 Error Interrupt Reg - write only */ 93 /* Force Event Error Interrupt Register- write only */ 94 /* RO Host Controller Version Register always reads as 0x2401 */ 95 96 /* Configurable properties */ 97 bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */ 98 uint32_t quirks; 99 uint8_t sd_spec_version; 100 uint8_t uhs_mode; 101 uint8_t vendor; /* For vendor specific functionality */ 102 }; 103 typedef struct SDHCIState SDHCIState; 104 105 #define SDHCI_VENDOR_NONE 0 106 #define SDHCI_VENDOR_IMX 1 107 108 /* 109 * Controller does not provide transfer-complete interrupt when not 110 * busy. 111 * 112 * NOTE: This definition is taken out of Linux kernel and so the 113 * original bit number is preserved 114 */ 115 #define SDHCI_QUIRK_NO_BUSY_IRQ BIT(14) 116 117 #define TYPE_PCI_SDHCI "sdhci-pci" 118 DECLARE_INSTANCE_CHECKER(SDHCIState, PCI_SDHCI, 119 TYPE_PCI_SDHCI) 120 121 #define TYPE_SYSBUS_SDHCI "generic-sdhci" 122 DECLARE_INSTANCE_CHECKER(SDHCIState, SYSBUS_SDHCI, 123 TYPE_SYSBUS_SDHCI) 124 125 #define TYPE_IMX_USDHC "imx-usdhc" 126 127 #define TYPE_S3C_SDHCI "s3c-sdhci" 128 129 #endif /* SDHCI_H */ 130