1 /* 2 * Allwinner (sun4i and above) SD Host Controller emulation 3 * 4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HW_SD_ALLWINNER_SDHOST_H 21 #define HW_SD_ALLWINNER_SDHOST_H 22 23 #include "qom/object.h" 24 #include "hw/sysbus.h" 25 #include "hw/sd/sd.h" 26 27 /** 28 * Object model types 29 * @{ 30 */ 31 32 /** Generic Allwinner SD Host Controller (abstract) */ 33 #define TYPE_AW_SDHOST "allwinner-sdhost" 34 35 /** Allwinner sun4i family (A10, A12) */ 36 #define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i" 37 38 /** Allwinner sun5i family and newer (A13, H2+, H3, etc) */ 39 #define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i" 40 41 /** @} */ 42 43 /** 44 * Object model macros 45 * @{ 46 */ 47 48 #define AW_SDHOST(obj) \ 49 OBJECT_CHECK(AwSdHostState, (obj), TYPE_AW_SDHOST) 50 #define AW_SDHOST_CLASS(klass) \ 51 OBJECT_CLASS_CHECK(AwSdHostClass, (klass), TYPE_AW_SDHOST) 52 #define AW_SDHOST_GET_CLASS(obj) \ 53 OBJECT_GET_CLASS(AwSdHostClass, (obj), TYPE_AW_SDHOST) 54 55 /** @} */ 56 57 /** 58 * Allwinner SD Host Controller object instance state. 59 */ 60 typedef struct AwSdHostState { 61 /*< private >*/ 62 SysBusDevice busdev; 63 /*< public >*/ 64 65 /** Secure Digital (SD) bus, which connects to SD card (if present) */ 66 SDBus sdbus; 67 68 /** Maps I/O registers in physical memory */ 69 MemoryRegion iomem; 70 71 /** Interrupt output signal to notify CPU */ 72 qemu_irq irq; 73 74 /** Number of bytes left in current DMA transfer */ 75 uint32_t transfer_cnt; 76 77 /** 78 * @name Hardware Registers 79 * @{ 80 */ 81 82 uint32_t global_ctl; /**< Global Control */ 83 uint32_t clock_ctl; /**< Clock Control */ 84 uint32_t timeout; /**< Timeout */ 85 uint32_t bus_width; /**< Bus Width */ 86 uint32_t block_size; /**< Block Size */ 87 uint32_t byte_count; /**< Byte Count */ 88 89 uint32_t command; /**< Command */ 90 uint32_t command_arg; /**< Command Argument */ 91 uint32_t response[4]; /**< Command Response */ 92 93 uint32_t irq_mask; /**< Interrupt Mask */ 94 uint32_t irq_status; /**< Raw Interrupt Status */ 95 uint32_t status; /**< Status */ 96 97 uint32_t fifo_wlevel; /**< FIFO Water Level */ 98 uint32_t fifo_func_sel; /**< FIFO Function Select */ 99 uint32_t debug_enable; /**< Debug Enable */ 100 uint32_t auto12_arg; /**< Auto Command 12 Argument */ 101 uint32_t newtiming_set; /**< SD New Timing Set */ 102 uint32_t newtiming_debug; /**< SD New Timing Debug */ 103 uint32_t hardware_rst; /**< Hardware Reset */ 104 uint32_t dmac; /**< Internal DMA Controller Control */ 105 uint32_t desc_base; /**< Descriptor List Base Address */ 106 uint32_t dmac_status; /**< Internal DMA Controller Status */ 107 uint32_t dmac_irq; /**< Internal DMA Controller IRQ Enable */ 108 uint32_t card_threshold; /**< Card Threshold Control */ 109 uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control */ 110 uint32_t response_crc; /**< Response CRC */ 111 uint32_t data_crc[8]; /**< Data CRC */ 112 uint32_t status_crc; /**< Status CRC */ 113 114 /** @} */ 115 116 } AwSdHostState; 117 118 /** 119 * Allwinner SD Host Controller class-level struct. 120 * 121 * This struct is filled by each sunxi device specific code 122 * such that the generic code can use this struct to support 123 * all devices. 124 */ 125 typedef struct AwSdHostClass { 126 /*< private >*/ 127 SysBusDeviceClass parent_class; 128 /*< public >*/ 129 130 /** Maximum buffer size in bytes per DMA descriptor */ 131 size_t max_desc_size; 132 133 } AwSdHostClass; 134 135 #endif /* HW_SD_ALLWINNER_SDHOST_H */ 136