1 #ifndef QEMU_HW_ESP_H 2 #define QEMU_HW_ESP_H 3 4 #include "hw/scsi/scsi.h" 5 #include "hw/sysbus.h" 6 7 /* esp.c */ 8 #define ESP_MAX_DEVS 7 9 typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len); 10 void esp_init(hwaddr espaddr, int it_shift, 11 ESPDMAMemoryReadWriteFunc dma_memory_read, 12 ESPDMAMemoryReadWriteFunc dma_memory_write, 13 void *dma_opaque, qemu_irq irq, qemu_irq *reset, 14 qemu_irq *dma_enable); 15 16 #define ESP_REGS 16 17 #define TI_BUFSZ 16 18 #define ESP_CMDBUF_SZ 32 19 20 typedef struct ESPState ESPState; 21 22 struct ESPState { 23 uint8_t rregs[ESP_REGS]; 24 uint8_t wregs[ESP_REGS]; 25 qemu_irq irq; 26 uint8_t chip_id; 27 bool tchi_written; 28 int32_t ti_size; 29 uint32_t ti_rptr, ti_wptr; 30 uint32_t status; 31 uint32_t dma; 32 uint8_t ti_buf[TI_BUFSZ]; 33 SCSIBus bus; 34 SCSIDevice *current_dev; 35 SCSIRequest *current_req; 36 uint8_t cmdbuf[ESP_CMDBUF_SZ]; 37 uint32_t cmdlen; 38 uint32_t do_cmd; 39 40 /* The amount of data left in the current DMA transfer. */ 41 uint32_t dma_left; 42 /* The size of the current DMA transfer. Zero if no transfer is in 43 progress. */ 44 uint32_t dma_counter; 45 int dma_enabled; 46 47 uint32_t async_len; 48 uint8_t *async_buf; 49 50 ESPDMAMemoryReadWriteFunc dma_memory_read; 51 ESPDMAMemoryReadWriteFunc dma_memory_write; 52 void *dma_opaque; 53 void (*dma_cb)(ESPState *s); 54 }; 55 56 #define TYPE_ESP "esp" 57 #define ESP_STATE(obj) OBJECT_CHECK(SysBusESPState, (obj), TYPE_ESP) 58 59 typedef struct { 60 /*< private >*/ 61 SysBusDevice parent_obj; 62 /*< public >*/ 63 64 MemoryRegion iomem; 65 uint32_t it_shift; 66 ESPState esp; 67 } SysBusESPState; 68 69 #define ESP_TCLO 0x0 70 #define ESP_TCMID 0x1 71 #define ESP_FIFO 0x2 72 #define ESP_CMD 0x3 73 #define ESP_RSTAT 0x4 74 #define ESP_WBUSID 0x4 75 #define ESP_RINTR 0x5 76 #define ESP_WSEL 0x5 77 #define ESP_RSEQ 0x6 78 #define ESP_WSYNTP 0x6 79 #define ESP_RFLAGS 0x7 80 #define ESP_WSYNO 0x7 81 #define ESP_CFG1 0x8 82 #define ESP_RRES1 0x9 83 #define ESP_WCCF 0x9 84 #define ESP_RRES2 0xa 85 #define ESP_WTEST 0xa 86 #define ESP_CFG2 0xb 87 #define ESP_CFG3 0xc 88 #define ESP_RES3 0xd 89 #define ESP_TCHI 0xe 90 #define ESP_RES4 0xf 91 92 #define CMD_DMA 0x80 93 #define CMD_CMD 0x7f 94 95 #define CMD_NOP 0x00 96 #define CMD_FLUSH 0x01 97 #define CMD_RESET 0x02 98 #define CMD_BUSRESET 0x03 99 #define CMD_TI 0x10 100 #define CMD_ICCS 0x11 101 #define CMD_MSGACC 0x12 102 #define CMD_PAD 0x18 103 #define CMD_SATN 0x1a 104 #define CMD_RSTATN 0x1b 105 #define CMD_SEL 0x41 106 #define CMD_SELATN 0x42 107 #define CMD_SELATNS 0x43 108 #define CMD_ENSEL 0x44 109 #define CMD_DISSEL 0x45 110 111 #define STAT_DO 0x00 112 #define STAT_DI 0x01 113 #define STAT_CD 0x02 114 #define STAT_ST 0x03 115 #define STAT_MO 0x06 116 #define STAT_MI 0x07 117 #define STAT_PIO_MASK 0x06 118 119 #define STAT_TC 0x10 120 #define STAT_PE 0x20 121 #define STAT_GE 0x40 122 #define STAT_INT 0x80 123 124 #define BUSID_DID 0x07 125 126 #define INTR_FC 0x08 127 #define INTR_BS 0x10 128 #define INTR_DC 0x20 129 #define INTR_RST 0x80 130 131 #define SEQ_0 0x0 132 #define SEQ_CD 0x4 133 134 #define CFG1_RESREPT 0x40 135 136 #define TCHI_FAS100A 0x4 137 #define TCHI_AM53C974 0x12 138 139 void esp_dma_enable(ESPState *s, int irq, int level); 140 void esp_request_cancelled(SCSIRequest *req); 141 void esp_command_complete(SCSIRequest *req, uint32_t status, size_t resid); 142 void esp_transfer_data(SCSIRequest *req, uint32_t len); 143 void esp_hard_reset(ESPState *s); 144 uint64_t esp_reg_read(ESPState *s, uint32_t saddr); 145 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val); 146 extern const VMStateDescription vmstate_esp; 147 148 #endif 149