1 #ifndef QEMU_HW_ESP_H 2 #define QEMU_HW_ESP_H 3 4 #include "hw/scsi/scsi.h" 5 #include "hw/sysbus.h" 6 #include "qemu/fifo8.h" 7 #include "qom/object.h" 8 9 /* esp.c */ 10 #define ESP_MAX_DEVS 7 11 typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len); 12 13 #define ESP_REGS 16 14 #define ESP_FIFO_SZ 16 15 #define ESP_CMDFIFO_SZ 32 16 17 typedef struct ESPState ESPState; 18 19 #define TYPE_ESP "esp" 20 OBJECT_DECLARE_SIMPLE_TYPE(ESPState, ESP) 21 22 struct ESPState { 23 DeviceState parent_obj; 24 25 uint8_t rregs[ESP_REGS]; 26 uint8_t wregs[ESP_REGS]; 27 qemu_irq irq; 28 qemu_irq drq_irq; 29 bool drq_state; 30 uint8_t chip_id; 31 bool tchi_written; 32 int32_t ti_size; 33 uint32_t status; 34 uint32_t dma; 35 Fifo8 fifo; 36 SCSIBus bus; 37 SCSIDevice *current_dev; 38 SCSIRequest *current_req; 39 Fifo8 cmdfifo; 40 uint8_t cmdfifo_cdb_offset; 41 uint8_t lun; 42 uint32_t do_cmd; 43 44 bool data_ready; 45 int dma_enabled; 46 47 uint32_t async_len; 48 uint8_t *async_buf; 49 50 ESPDMAMemoryReadWriteFunc dma_memory_read; 51 ESPDMAMemoryReadWriteFunc dma_memory_write; 52 void *dma_opaque; 53 void (*dma_cb)(ESPState *s); 54 55 uint8_t mig_version_id; 56 57 /* Legacy fields for vmstate_esp version < 5 */ 58 uint32_t mig_dma_left; 59 uint32_t mig_deferred_status; 60 bool mig_deferred_complete; 61 uint32_t mig_ti_rptr, mig_ti_wptr; 62 uint8_t mig_ti_buf[ESP_FIFO_SZ]; 63 uint8_t mig_cmdbuf[ESP_CMDFIFO_SZ]; 64 uint32_t mig_cmdlen; 65 66 uint8_t mig_ti_cmd; 67 }; 68 69 #define TYPE_SYSBUS_ESP "sysbus-esp" 70 OBJECT_DECLARE_SIMPLE_TYPE(SysBusESPState, SYSBUS_ESP) 71 72 struct SysBusESPState { 73 /*< private >*/ 74 SysBusDevice parent_obj; 75 /*< public >*/ 76 77 MemoryRegion iomem; 78 MemoryRegion pdma; 79 uint32_t it_shift; 80 ESPState esp; 81 }; 82 83 #define ESP_TCLO 0x0 84 #define ESP_TCMID 0x1 85 #define ESP_FIFO 0x2 86 #define ESP_CMD 0x3 87 #define ESP_RSTAT 0x4 88 #define ESP_WBUSID 0x4 89 #define ESP_RINTR 0x5 90 #define ESP_WSEL 0x5 91 #define ESP_RSEQ 0x6 92 #define ESP_WSYNTP 0x6 93 #define ESP_RFLAGS 0x7 94 #define ESP_WSYNO 0x7 95 #define ESP_CFG1 0x8 96 #define ESP_RRES1 0x9 97 #define ESP_WCCF 0x9 98 #define ESP_RRES2 0xa 99 #define ESP_WTEST 0xa 100 #define ESP_CFG2 0xb 101 #define ESP_CFG3 0xc 102 #define ESP_RES3 0xd 103 #define ESP_TCHI 0xe 104 #define ESP_RES4 0xf 105 106 #define CMD_DMA 0x80 107 #define CMD_CMD 0x7f 108 109 #define CMD_NOP 0x00 110 #define CMD_FLUSH 0x01 111 #define CMD_RESET 0x02 112 #define CMD_BUSRESET 0x03 113 #define CMD_TI 0x10 114 #define CMD_ICCS 0x11 115 #define CMD_MSGACC 0x12 116 #define CMD_PAD 0x18 117 #define CMD_SATN 0x1a 118 #define CMD_RSTATN 0x1b 119 #define CMD_SEL 0x41 120 #define CMD_SELATN 0x42 121 #define CMD_SELATNS 0x43 122 #define CMD_ENSEL 0x44 123 #define CMD_DISSEL 0x45 124 125 #define STAT_DO 0x00 126 #define STAT_DI 0x01 127 #define STAT_CD 0x02 128 #define STAT_ST 0x03 129 #define STAT_MO 0x06 130 #define STAT_MI 0x07 131 #define STAT_PIO_MASK 0x06 132 133 #define STAT_TC 0x10 134 #define STAT_PE 0x20 135 #define STAT_GE 0x40 136 #define STAT_INT 0x80 137 138 #define BUSID_DID 0x07 139 140 #define INTR_FC 0x08 141 #define INTR_BS 0x10 142 #define INTR_DC 0x20 143 #define INTR_RST 0x80 144 145 #define SEQ_0 0x0 146 #define SEQ_MO 0x1 147 #define SEQ_CD 0x4 148 149 #define CFG1_RESREPT 0x40 150 151 #define TCHI_FAS100A 0x4 152 #define TCHI_AM53C974 0x12 153 154 void esp_dma_enable(ESPState *s, int irq, int level); 155 void esp_request_cancelled(SCSIRequest *req); 156 void esp_command_complete(SCSIRequest *req, size_t resid); 157 void esp_transfer_data(SCSIRequest *req, uint32_t len); 158 void esp_hard_reset(ESPState *s); 159 uint64_t esp_reg_read(ESPState *s, uint32_t saddr); 160 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val); 161 extern const VMStateDescription vmstate_esp; 162 int esp_pre_save(void *opaque); 163 164 #endif 165