1 #ifndef QEMU_HW_ESP_H 2 #define QEMU_HW_ESP_H 3 4 #include "hw/scsi/scsi.h" 5 6 /* esp.c */ 7 #define ESP_MAX_DEVS 7 8 typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len); 9 void esp_init(hwaddr espaddr, int it_shift, 10 ESPDMAMemoryReadWriteFunc dma_memory_read, 11 ESPDMAMemoryReadWriteFunc dma_memory_write, 12 void *dma_opaque, qemu_irq irq, qemu_irq *reset, 13 qemu_irq *dma_enable); 14 15 #define ESP_REGS 16 16 #define TI_BUFSZ 16 17 18 typedef struct ESPState ESPState; 19 20 struct ESPState { 21 uint8_t rregs[ESP_REGS]; 22 uint8_t wregs[ESP_REGS]; 23 qemu_irq irq; 24 uint8_t chip_id; 25 int32_t ti_size; 26 uint32_t ti_rptr, ti_wptr; 27 uint32_t status; 28 uint32_t dma; 29 uint8_t ti_buf[TI_BUFSZ]; 30 SCSIBus bus; 31 SCSIDevice *current_dev; 32 SCSIRequest *current_req; 33 uint8_t cmdbuf[TI_BUFSZ]; 34 uint32_t cmdlen; 35 uint32_t do_cmd; 36 37 /* The amount of data left in the current DMA transfer. */ 38 uint32_t dma_left; 39 /* The size of the current DMA transfer. Zero if no transfer is in 40 progress. */ 41 uint32_t dma_counter; 42 int dma_enabled; 43 44 uint32_t async_len; 45 uint8_t *async_buf; 46 47 ESPDMAMemoryReadWriteFunc dma_memory_read; 48 ESPDMAMemoryReadWriteFunc dma_memory_write; 49 void *dma_opaque; 50 void (*dma_cb)(ESPState *s); 51 }; 52 53 #define ESP_TCLO 0x0 54 #define ESP_TCMID 0x1 55 #define ESP_FIFO 0x2 56 #define ESP_CMD 0x3 57 #define ESP_RSTAT 0x4 58 #define ESP_WBUSID 0x4 59 #define ESP_RINTR 0x5 60 #define ESP_WSEL 0x5 61 #define ESP_RSEQ 0x6 62 #define ESP_WSYNTP 0x6 63 #define ESP_RFLAGS 0x7 64 #define ESP_WSYNO 0x7 65 #define ESP_CFG1 0x8 66 #define ESP_RRES1 0x9 67 #define ESP_WCCF 0x9 68 #define ESP_RRES2 0xa 69 #define ESP_WTEST 0xa 70 #define ESP_CFG2 0xb 71 #define ESP_CFG3 0xc 72 #define ESP_RES3 0xd 73 #define ESP_TCHI 0xe 74 #define ESP_RES4 0xf 75 76 #define CMD_DMA 0x80 77 #define CMD_CMD 0x7f 78 79 #define CMD_NOP 0x00 80 #define CMD_FLUSH 0x01 81 #define CMD_RESET 0x02 82 #define CMD_BUSRESET 0x03 83 #define CMD_TI 0x10 84 #define CMD_ICCS 0x11 85 #define CMD_MSGACC 0x12 86 #define CMD_PAD 0x18 87 #define CMD_SATN 0x1a 88 #define CMD_RSTATN 0x1b 89 #define CMD_SEL 0x41 90 #define CMD_SELATN 0x42 91 #define CMD_SELATNS 0x43 92 #define CMD_ENSEL 0x44 93 #define CMD_DISSEL 0x45 94 95 #define STAT_DO 0x00 96 #define STAT_DI 0x01 97 #define STAT_CD 0x02 98 #define STAT_ST 0x03 99 #define STAT_MO 0x06 100 #define STAT_MI 0x07 101 #define STAT_PIO_MASK 0x06 102 103 #define STAT_TC 0x10 104 #define STAT_PE 0x20 105 #define STAT_GE 0x40 106 #define STAT_INT 0x80 107 108 #define BUSID_DID 0x07 109 110 #define INTR_FC 0x08 111 #define INTR_BS 0x10 112 #define INTR_DC 0x20 113 #define INTR_RST 0x80 114 115 #define SEQ_0 0x0 116 #define SEQ_CD 0x4 117 118 #define CFG1_RESREPT 0x40 119 120 #define TCHI_FAS100A 0x4 121 #define TCHI_AM53C974 0x12 122 123 void esp_dma_enable(ESPState *s, int irq, int level); 124 void esp_request_cancelled(SCSIRequest *req); 125 void esp_command_complete(SCSIRequest *req, uint32_t status, size_t resid); 126 void esp_transfer_data(SCSIRequest *req, uint32_t len); 127 void esp_hard_reset(ESPState *s); 128 uint64_t esp_reg_read(ESPState *s, uint32_t saddr); 129 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val); 130 extern const VMStateDescription vmstate_esp; 131 132 #endif 133