1 /* 2 * s390 PCI BUS definitions 3 * 4 * Copyright 2014 IBM Corp. 5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com> 6 * Hong Bo Li <lihbbj@cn.ibm.com> 7 * Yi Min Zhao <zyimin@cn.ibm.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or (at 10 * your option) any later version. See the COPYING file in the top-level 11 * directory. 12 */ 13 14 #ifndef HW_S390_PCI_BUS_H 15 #define HW_S390_PCI_BUS_H 16 17 #include "hw/pci/pci.h" 18 #include "hw/pci/pci_host.h" 19 #include "hw/s390x/sclp.h" 20 #include "hw/s390x/s390_flic.h" 21 #include "hw/s390x/css.h" 22 #include "hw/s390x/s390-pci-clp.h" 23 #include "qom/object.h" 24 25 #define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost" 26 #define TYPE_S390_PCI_BUS "s390-pcibus" 27 #define TYPE_S390_PCI_DEVICE "zpci" 28 #define TYPE_S390_PCI_IOMMU "s390-pci-iommu" 29 #define TYPE_S390_IOMMU_MEMORY_REGION "s390-iommu-memory-region" 30 #define FH_MASK_ENABLE 0x80000000 31 #define FH_MASK_INSTANCE 0x7f000000 32 #define FH_MASK_SHM 0x00ff0000 33 #define FH_MASK_INDEX 0x0000ffff 34 #define FH_SHM_VFIO 0x00010000 35 #define FH_SHM_EMUL 0x00020000 36 #define ZPCI_MAX_FID 0xffffffff 37 #define ZPCI_MAX_UID 0xffff 38 #define UID_UNDEFINED 0 39 #define UID_CHECKING_ENABLED 0x01 40 41 OBJECT_DECLARE_SIMPLE_TYPE(S390pciState, S390_PCI_HOST_BRIDGE) 42 OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBus, S390_PCI_BUS) 43 OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBusDevice, S390_PCI_DEVICE) 44 OBJECT_DECLARE_SIMPLE_TYPE(S390PCIIOMMU, S390_PCI_IOMMU) 45 46 #define HP_EVENT_TO_CONFIGURED 0x0301 47 #define HP_EVENT_RESERVED_TO_STANDBY 0x0302 48 #define HP_EVENT_DECONFIGURE_REQUEST 0x0303 49 #define HP_EVENT_CONFIGURED_TO_STBRES 0x0304 50 #define HP_EVENT_STANDBY_TO_RESERVED 0x0308 51 52 #define ERR_EVENT_INVALAS 0x1 53 #define ERR_EVENT_OORANGE 0x2 54 #define ERR_EVENT_INVALTF 0x3 55 #define ERR_EVENT_TPROTE 0x4 56 #define ERR_EVENT_APROTE 0x5 57 #define ERR_EVENT_KEYE 0x6 58 #define ERR_EVENT_INVALTE 0x7 59 #define ERR_EVENT_INVALTL 0x8 60 #define ERR_EVENT_TT 0x9 61 #define ERR_EVENT_INVALMS 0xa 62 #define ERR_EVENT_SERR 0xb 63 #define ERR_EVENT_NOMSI 0x10 64 #define ERR_EVENT_INVALBV 0x11 65 #define ERR_EVENT_AIBV 0x12 66 #define ERR_EVENT_AIRERR 0x13 67 #define ERR_EVENT_FMBA 0x2a 68 #define ERR_EVENT_FMBUP 0x2b 69 #define ERR_EVENT_FMBPRO 0x2c 70 #define ERR_EVENT_CCONF 0x30 71 #define ERR_EVENT_SERVAC 0x3a 72 #define ERR_EVENT_PERMERR 0x3b 73 74 #define ERR_EVENT_Q_BIT 0x2 75 #define ERR_EVENT_MVN_OFFSET 16 76 77 #define ZPCI_MSI_VEC_BITS 11 78 #define ZPCI_MSI_VEC_MASK 0x7ff 79 80 #define ZPCI_MSI_ADDR 0xfe00000000000000ULL 81 #define ZPCI_SDMA_ADDR 0x100000000ULL 82 #define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL 83 84 #define PAGE_SHIFT 12 85 #define PAGE_SIZE (1 << PAGE_SHIFT) 86 #define PAGE_MASK (~(PAGE_SIZE-1)) 87 #define PAGE_DEFAULT_ACC 0 88 #define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4) 89 90 /* I/O Translation Anchor (IOTA) */ 91 enum ZpciIoatDtype { 92 ZPCI_IOTA_STO = 0, 93 ZPCI_IOTA_RTTO = 1, 94 ZPCI_IOTA_RSTO = 2, 95 ZPCI_IOTA_RFTO = 3, 96 ZPCI_IOTA_PFAA = 4, 97 ZPCI_IOTA_IOPFAA = 5, 98 ZPCI_IOTA_IOPTO = 7 99 }; 100 101 #define ZPCI_IOTA_IOT_ENABLED 0x800ULL 102 #define ZPCI_IOTA_DT_ST (ZPCI_IOTA_STO << 2) 103 #define ZPCI_IOTA_DT_RT (ZPCI_IOTA_RTTO << 2) 104 #define ZPCI_IOTA_DT_RS (ZPCI_IOTA_RSTO << 2) 105 #define ZPCI_IOTA_DT_RF (ZPCI_IOTA_RFTO << 2) 106 #define ZPCI_IOTA_DT_PF (ZPCI_IOTA_PFAA << 2) 107 #define ZPCI_IOTA_FS_4K 0 108 #define ZPCI_IOTA_FS_1M 1 109 #define ZPCI_IOTA_FS_2G 2 110 #define ZPCI_KEY (PAGE_DEFAULT_KEY << 5) 111 112 #define ZPCI_IOTA_STO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST) 113 #define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT) 114 #define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS) 115 #define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF) 116 #define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\ 117 ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G) 118 119 /* I/O Region and segment tables */ 120 #define ZPCI_INDEX_MASK 0x7ffULL 121 122 #define ZPCI_TABLE_TYPE_MASK 0xc 123 #define ZPCI_TABLE_TYPE_RFX 0xc 124 #define ZPCI_TABLE_TYPE_RSX 0x8 125 #define ZPCI_TABLE_TYPE_RTX 0x4 126 #define ZPCI_TABLE_TYPE_SX 0x0 127 128 #define ZPCI_TABLE_LEN_RFX 0x3 129 #define ZPCI_TABLE_LEN_RSX 0x3 130 #define ZPCI_TABLE_LEN_RTX 0x3 131 132 #define ZPCI_TABLE_OFFSET_MASK 0xc0 133 #define ZPCI_TABLE_SIZE 0x4000 134 #define ZPCI_TABLE_ALIGN ZPCI_TABLE_SIZE 135 #define ZPCI_TABLE_ENTRY_SIZE (sizeof(unsigned long)) 136 #define ZPCI_TABLE_ENTRIES (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE) 137 138 #define ZPCI_TABLE_BITS 11 139 #define ZPCI_PT_BITS 8 140 #define ZPCI_ST_SHIFT (ZPCI_PT_BITS + PAGE_SHIFT) 141 #define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS) 142 143 #define ZPCI_RTE_FLAG_MASK 0x3fffULL 144 #define ZPCI_RTE_ADDR_MASK (~ZPCI_RTE_FLAG_MASK) 145 #define ZPCI_STE_FLAG_MASK 0x7ffULL 146 #define ZPCI_STE_ADDR_MASK (~ZPCI_STE_FLAG_MASK) 147 148 #define ZPCI_SFAA_MASK (~((1ULL << 20) - 1)) 149 150 /* I/O Page tables */ 151 #define ZPCI_PTE_VALID_MASK 0x400 152 #define ZPCI_PTE_INVALID 0x400 153 #define ZPCI_PTE_VALID 0x000 154 #define ZPCI_PT_SIZE 0x800 155 #define ZPCI_PT_ALIGN ZPCI_PT_SIZE 156 #define ZPCI_PT_ENTRIES (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE) 157 #define ZPCI_PT_MASK (ZPCI_PT_ENTRIES - 1) 158 159 #define ZPCI_PTE_FLAG_MASK 0xfffULL 160 #define ZPCI_PTE_ADDR_MASK (~ZPCI_PTE_FLAG_MASK) 161 162 /* Shared bits */ 163 #define ZPCI_TABLE_VALID 0x00 164 #define ZPCI_TABLE_INVALID 0x20 165 #define ZPCI_TABLE_PROTECTED 0x200 166 #define ZPCI_TABLE_UNPROTECTED 0x000 167 #define ZPCI_TABLE_FC 0x400 168 169 #define ZPCI_TABLE_VALID_MASK 0x20 170 #define ZPCI_TABLE_PROT_MASK 0x200 171 172 #define ZPCI_ETT_RT 1 173 #define ZPCI_ETT_ST 0 174 #define ZPCI_ETT_PT -1 175 176 /* PCI Function States 177 * 178 * reserved: default; device has just been plugged or is in progress of being 179 * unplugged 180 * standby: device is present but not configured; transition from any 181 * configured state/to this state via sclp configure/deconfigure 182 * 183 * The following states make up the "configured" meta-state: 184 * disabled: device is configured but not enabled; transition between this 185 * state and enabled via clp enable/disable 186 * enbaled: device is ready for use; transition to disabled via clp disable; 187 * may enter an error state 188 * blocked: ignore all DMA and interrupts; transition back to enabled or from 189 * error state via mpcifc 190 * error: an error occurred; transition back to enabled via mpcifc 191 * permanent error: an unrecoverable error occurred; transition to standby via 192 * sclp deconfigure 193 */ 194 typedef enum { 195 ZPCI_FS_RESERVED, 196 ZPCI_FS_STANDBY, 197 ZPCI_FS_DISABLED, 198 ZPCI_FS_ENABLED, 199 ZPCI_FS_BLOCKED, 200 ZPCI_FS_ERROR, 201 ZPCI_FS_PERMANENT_ERROR, 202 } ZpciState; 203 204 typedef struct SeiContainer { 205 QTAILQ_ENTRY(SeiContainer) link; 206 uint32_t fid; 207 uint32_t fh; 208 uint8_t cc; 209 uint16_t pec; 210 uint64_t faddr; 211 uint32_t e; 212 } SeiContainer; 213 214 typedef struct PciCcdfErr { 215 uint32_t reserved1; 216 uint32_t fh; 217 uint32_t fid; 218 uint32_t e; 219 uint64_t faddr; 220 uint32_t reserved3; 221 uint16_t reserved4; 222 uint16_t pec; 223 } QEMU_PACKED PciCcdfErr; 224 225 typedef struct PciCcdfAvail { 226 uint32_t reserved1; 227 uint32_t fh; 228 uint32_t fid; 229 uint32_t reserved2; 230 uint32_t reserved3; 231 uint32_t reserved4; 232 uint32_t reserved5; 233 uint16_t reserved6; 234 uint16_t pec; 235 } QEMU_PACKED PciCcdfAvail; 236 237 typedef struct ChscSeiNt2Res { 238 uint16_t length; 239 uint16_t code; 240 uint16_t reserved1; 241 uint8_t reserved2; 242 uint8_t nt; 243 uint8_t flags; 244 uint8_t reserved3; 245 uint8_t reserved4; 246 uint8_t cc; 247 uint32_t reserved5[13]; 248 uint8_t ccdf[4016]; 249 } QEMU_PACKED ChscSeiNt2Res; 250 251 typedef struct S390MsixInfo { 252 uint8_t table_bar; 253 uint8_t pba_bar; 254 uint16_t entries; 255 uint32_t table_offset; 256 uint32_t pba_offset; 257 } S390MsixInfo; 258 259 typedef struct S390IOTLBEntry { 260 uint64_t iova; 261 uint64_t translated_addr; 262 uint64_t len; 263 uint64_t perm; 264 } S390IOTLBEntry; 265 266 typedef struct S390PCIDMACount { 267 int id; 268 int users; 269 uint32_t avail; 270 QTAILQ_ENTRY(S390PCIDMACount) link; 271 } S390PCIDMACount; 272 273 struct S390PCIIOMMU { 274 Object parent_obj; 275 S390PCIBusDevice *pbdev; 276 AddressSpace as; 277 MemoryRegion mr; 278 IOMMUMemoryRegion iommu_mr; 279 bool enabled; 280 uint64_t g_iota; 281 uint64_t pba; 282 uint64_t pal; 283 GHashTable *iotlb; 284 S390PCIDMACount *dma_limit; 285 }; 286 287 typedef struct S390PCIIOMMUTable { 288 uint64_t key; 289 S390PCIIOMMU *iommu[PCI_SLOT_MAX]; 290 } S390PCIIOMMUTable; 291 292 /* Function Measurement Block */ 293 #define DEFAULT_MUI 4000 294 #define UPDATE_U_BIT 0x1ULL 295 #define FMBK_MASK 0xfULL 296 297 typedef struct ZpciFmbFmt0 { 298 uint64_t dma_rbytes; 299 uint64_t dma_wbytes; 300 } ZpciFmbFmt0; 301 302 #define ZPCI_FMB_CNT_LD 0 303 #define ZPCI_FMB_CNT_ST 1 304 #define ZPCI_FMB_CNT_STB 2 305 #define ZPCI_FMB_CNT_RPCIT 3 306 #define ZPCI_FMB_CNT_MAX 4 307 308 #define ZPCI_FMB_FORMAT 0 309 310 typedef struct ZpciFmb { 311 uint32_t format; 312 uint32_t sample; 313 uint64_t last_update; 314 uint64_t counter[ZPCI_FMB_CNT_MAX]; 315 ZpciFmbFmt0 fmt0; 316 } ZpciFmb; 317 QEMU_BUILD_BUG_MSG(offsetof(ZpciFmb, fmt0) != 48, "padding in ZpciFmb"); 318 319 #define ZPCI_DEFAULT_FN_GRP 0x20 320 typedef struct S390PCIGroup { 321 ClpRspQueryPciGrp zpci_group; 322 int id; 323 QTAILQ_ENTRY(S390PCIGroup) link; 324 } S390PCIGroup; 325 S390PCIGroup *s390_group_create(int id); 326 S390PCIGroup *s390_group_find(int id); 327 328 struct S390PCIBusDevice { 329 DeviceState qdev; 330 PCIDevice *pdev; 331 ZpciState state; 332 char *target; 333 uint16_t uid; 334 uint32_t idx; 335 uint32_t fh; 336 uint32_t fid; 337 bool fid_defined; 338 uint64_t fmb_addr; 339 ZpciFmb fmb; 340 QEMUTimer *fmb_timer; 341 uint8_t isc; 342 uint16_t noi; 343 uint16_t maxstbl; 344 uint8_t sum; 345 S390PCIGroup *pci_group; 346 ClpRspQueryPci zpci_fn; 347 S390MsixInfo msix; 348 AdapterRoutes routes; 349 S390PCIIOMMU *iommu; 350 MemoryRegion msix_notify_mr; 351 IndAddr *summary_ind; 352 IndAddr *indicator; 353 bool pci_unplug_request_processed; 354 bool unplug_requested; 355 QTAILQ_ENTRY(S390PCIBusDevice) link; 356 }; 357 358 struct S390PCIBus { 359 BusState qbus; 360 }; 361 362 struct S390pciState { 363 PCIHostState parent_obj; 364 uint32_t next_idx; 365 int bus_no; 366 S390PCIBus *bus; 367 GHashTable *iommu_table; 368 GHashTable *zpci_table; 369 QTAILQ_HEAD(, SeiContainer) pending_sei; 370 QTAILQ_HEAD(, S390PCIBusDevice) zpci_devs; 371 QTAILQ_HEAD(, S390PCIDMACount) zpci_dma_limit; 372 QTAILQ_HEAD(, S390PCIGroup) zpci_groups; 373 }; 374 375 S390pciState *s390_get_phb(void); 376 int pci_chsc_sei_nt2_get_event(void *res); 377 int pci_chsc_sei_nt2_have_event(void); 378 void s390_pci_sclp_configure(SCCB *sccb); 379 void s390_pci_sclp_deconfigure(SCCB *sccb); 380 void s390_pci_iommu_enable(S390PCIIOMMU *iommu); 381 void s390_pci_iommu_disable(S390PCIIOMMU *iommu); 382 void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid, 383 uint64_t faddr, uint32_t e); 384 uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr, 385 S390IOTLBEntry *entry); 386 S390PCIBusDevice *s390_pci_find_dev_by_idx(S390pciState *s, uint32_t idx); 387 S390PCIBusDevice *s390_pci_find_dev_by_fh(S390pciState *s, uint32_t fh); 388 S390PCIBusDevice *s390_pci_find_dev_by_fid(S390pciState *s, uint32_t fid); 389 S390PCIBusDevice *s390_pci_find_dev_by_target(S390pciState *s, 390 const char *target); 391 S390PCIBusDevice *s390_pci_find_next_avail_dev(S390pciState *s, 392 S390PCIBusDevice *pbdev); 393 394 #endif 395