19a5b40b8SAnup Patel /* 29a5b40b8SAnup Patel * Goldfish virtual platform RTC 39a5b40b8SAnup Patel * 49a5b40b8SAnup Patel * Copyright (C) 2019 Western Digital Corporation or its affiliates. 59a5b40b8SAnup Patel * 69a5b40b8SAnup Patel * For more details on Google Goldfish virtual platform refer: 79a5b40b8SAnup Patel * https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT 89a5b40b8SAnup Patel * 99a5b40b8SAnup Patel * This program is free software; you can redistribute it and/or modify it 109a5b40b8SAnup Patel * under the terms and conditions of the GNU General Public License, 119a5b40b8SAnup Patel * version 2 or later, as published by the Free Software Foundation. 129a5b40b8SAnup Patel * 139a5b40b8SAnup Patel * This program is distributed in the hope it will be useful, but WITHOUT 149a5b40b8SAnup Patel * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 159a5b40b8SAnup Patel * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 169a5b40b8SAnup Patel * more details. 179a5b40b8SAnup Patel * 189a5b40b8SAnup Patel * You should have received a copy of the GNU General Public License along with 199a5b40b8SAnup Patel * this program. If not, see <http://www.gnu.org/licenses/>. 209a5b40b8SAnup Patel */ 219a5b40b8SAnup Patel 229a5b40b8SAnup Patel #ifndef HW_RTC_GOLDFISH_RTC_H 239a5b40b8SAnup Patel #define HW_RTC_GOLDFISH_RTC_H 249a5b40b8SAnup Patel 259a5b40b8SAnup Patel #include "hw/sysbus.h" 26*db1015e9SEduardo Habkost #include "qom/object.h" 279a5b40b8SAnup Patel 289a5b40b8SAnup Patel #define TYPE_GOLDFISH_RTC "goldfish_rtc" 29*db1015e9SEduardo Habkost typedef struct GoldfishRTCState GoldfishRTCState; 309a5b40b8SAnup Patel #define GOLDFISH_RTC(obj) \ 319a5b40b8SAnup Patel OBJECT_CHECK(GoldfishRTCState, (obj), TYPE_GOLDFISH_RTC) 329a5b40b8SAnup Patel 33*db1015e9SEduardo Habkost struct GoldfishRTCState { 349a5b40b8SAnup Patel SysBusDevice parent_obj; 359a5b40b8SAnup Patel 369a5b40b8SAnup Patel MemoryRegion iomem; 379a5b40b8SAnup Patel QEMUTimer *timer; 389a5b40b8SAnup Patel qemu_irq irq; 399a5b40b8SAnup Patel 409a5b40b8SAnup Patel uint64_t tick_offset; 419a5b40b8SAnup Patel uint64_t tick_offset_vmstate; 429a5b40b8SAnup Patel uint64_t alarm_next; 439a5b40b8SAnup Patel uint32_t alarm_running; 449a5b40b8SAnup Patel uint32_t irq_pending; 459a5b40b8SAnup Patel uint32_t irq_enabled; 468380b3a4SJessica Clarke uint32_t time_high; 47*db1015e9SEduardo Habkost }; 489a5b40b8SAnup Patel 499a5b40b8SAnup Patel #endif 50