xref: /openbmc/qemu/include/hw/riscv/virt.h (revision eb85394f)
1 /*
2  * QEMU RISC-V VirtIO machine interface
3  *
4  * Copyright (c) 2017 SiFive, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2 or later, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 #ifndef HW_RISCV_VIRT_H
20 #define HW_RISCV_VIRT_H
21 
22 #include "hw/riscv/riscv_hart.h"
23 #include "hw/sysbus.h"
24 #include "hw/block/flash.h"
25 #include "qom/object.h"
26 
27 #define VIRT_CPUS_MAX 8
28 #define VIRT_SOCKETS_MAX 8
29 
30 #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
31 typedef struct RISCVVirtState RISCVVirtState;
32 DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE,
33                          TYPE_RISCV_VIRT_MACHINE)
34 
35 struct RISCVVirtState {
36     /*< private >*/
37     MachineState parent;
38 
39     /*< public >*/
40     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
41     DeviceState *plic[VIRT_SOCKETS_MAX];
42     PFlashCFI01 *flash[2];
43 
44     void *fdt;
45     int fdt_size;
46 };
47 
48 enum {
49     VIRT_DEBUG,
50     VIRT_MROM,
51     VIRT_TEST,
52     VIRT_RTC,
53     VIRT_CLINT,
54     VIRT_PLIC,
55     VIRT_UART0,
56     VIRT_VIRTIO,
57     VIRT_FLASH,
58     VIRT_DRAM,
59     VIRT_PCIE_MMIO,
60     VIRT_PCIE_PIO,
61     VIRT_PCIE_ECAM
62 };
63 
64 enum {
65     UART0_IRQ = 10,
66     RTC_IRQ = 11,
67     VIRTIO_IRQ = 1, /* 1 to 8 */
68     VIRTIO_COUNT = 8,
69     PCIE_IRQ = 0x20, /* 32 to 35 */
70     VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
71 };
72 
73 #define VIRT_PLIC_HART_CONFIG "MS"
74 #define VIRT_PLIC_NUM_SOURCES 127
75 #define VIRT_PLIC_NUM_PRIORITIES 7
76 #define VIRT_PLIC_PRIORITY_BASE 0x04
77 #define VIRT_PLIC_PENDING_BASE 0x1000
78 #define VIRT_PLIC_ENABLE_BASE 0x2000
79 #define VIRT_PLIC_ENABLE_STRIDE 0x80
80 #define VIRT_PLIC_CONTEXT_BASE 0x200000
81 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000
82 #define VIRT_PLIC_SIZE(__num_context) \
83     (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
84 
85 #define FDT_PCI_ADDR_CELLS    3
86 #define FDT_PCI_INT_CELLS     1
87 #define FDT_PLIC_ADDR_CELLS   0
88 #define FDT_PLIC_INT_CELLS    1
89 #define FDT_INT_MAP_WIDTH     (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
90                                FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
91 
92 #if defined(TARGET_RISCV32)
93 #define VIRT_CPU TYPE_RISCV_CPU_BASE32
94 #elif defined(TARGET_RISCV64)
95 #define VIRT_CPU TYPE_RISCV_CPU_BASE64
96 #endif
97 
98 #endif
99