1 /* 2 * QEMU RISC-V VirtIO machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_RISCV_VIRT_H 20 #define HW_RISCV_VIRT_H 21 22 #include "hw/riscv/riscv_hart.h" 23 #include "hw/sysbus.h" 24 #include "hw/block/flash.h" 25 #include "qom/object.h" 26 27 #define VIRT_CPUS_MAX 32 28 #define VIRT_SOCKETS_MAX 8 29 30 #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 31 typedef struct RISCVVirtState RISCVVirtState; 32 DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE, 33 TYPE_RISCV_VIRT_MACHINE) 34 35 typedef enum RISCVVirtAIAType { 36 VIRT_AIA_TYPE_NONE = 0, 37 VIRT_AIA_TYPE_APLIC, 38 } RISCVVirtAIAType; 39 40 struct RISCVVirtState { 41 /*< private >*/ 42 MachineState parent; 43 44 /*< public >*/ 45 RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; 46 DeviceState *irqchip[VIRT_SOCKETS_MAX]; 47 PFlashCFI01 *flash[2]; 48 FWCfgState *fw_cfg; 49 50 int fdt_size; 51 bool have_aclint; 52 RISCVVirtAIAType aia_type; 53 }; 54 55 enum { 56 VIRT_DEBUG, 57 VIRT_MROM, 58 VIRT_TEST, 59 VIRT_RTC, 60 VIRT_CLINT, 61 VIRT_ACLINT_SSWI, 62 VIRT_PLIC, 63 VIRT_APLIC_M, 64 VIRT_APLIC_S, 65 VIRT_UART0, 66 VIRT_VIRTIO, 67 VIRT_FW_CFG, 68 VIRT_FLASH, 69 VIRT_DRAM, 70 VIRT_PCIE_MMIO, 71 VIRT_PCIE_PIO, 72 VIRT_PCIE_ECAM 73 }; 74 75 enum { 76 UART0_IRQ = 10, 77 RTC_IRQ = 11, 78 VIRTIO_IRQ = 1, /* 1 to 8 */ 79 VIRTIO_COUNT = 8, 80 PCIE_IRQ = 0x20, /* 32 to 35 */ 81 VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */ 82 }; 83 84 #define VIRT_IRQCHIP_NUM_SOURCES 127 85 #define VIRT_IRQCHIP_NUM_PRIO_BITS 3 86 87 #define VIRT_PLIC_PRIORITY_BASE 0x04 88 #define VIRT_PLIC_PENDING_BASE 0x1000 89 #define VIRT_PLIC_ENABLE_BASE 0x2000 90 #define VIRT_PLIC_ENABLE_STRIDE 0x80 91 #define VIRT_PLIC_CONTEXT_BASE 0x200000 92 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 93 #define VIRT_PLIC_SIZE(__num_context) \ 94 (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) 95 96 #define FDT_PCI_ADDR_CELLS 3 97 #define FDT_PCI_INT_CELLS 1 98 #define FDT_PLIC_INT_CELLS 1 99 #define FDT_APLIC_INT_CELLS 2 100 #define FDT_MAX_INT_CELLS 2 101 #define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 102 1 + FDT_MAX_INT_CELLS) 103 #define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 104 1 + FDT_PLIC_INT_CELLS) 105 #define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 106 1 + FDT_APLIC_INT_CELLS) 107 108 #endif 109