1 /* 2 * QEMU RISC-V VirtIO machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_RISCV_VIRT_H 20 #define HW_RISCV_VIRT_H 21 22 #include "hw/riscv/riscv_hart.h" 23 #include "hw/sysbus.h" 24 #include "hw/block/flash.h" 25 #include "qom/object.h" 26 27 #define VIRT_CPUS_MAX_BITS 9 28 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) 29 #define VIRT_SOCKETS_MAX_BITS 2 30 #define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS) 31 32 #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 33 typedef struct RISCVVirtState RISCVVirtState; 34 DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE, 35 TYPE_RISCV_VIRT_MACHINE) 36 37 typedef enum RISCVVirtAIAType { 38 VIRT_AIA_TYPE_NONE = 0, 39 VIRT_AIA_TYPE_APLIC, 40 VIRT_AIA_TYPE_APLIC_IMSIC, 41 } RISCVVirtAIAType; 42 43 struct RISCVVirtState { 44 /*< private >*/ 45 MachineState parent; 46 47 /*< public >*/ 48 Notifier machine_done; 49 RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; 50 DeviceState *irqchip[VIRT_SOCKETS_MAX]; 51 PFlashCFI01 *flash[2]; 52 FWCfgState *fw_cfg; 53 54 int fdt_size; 55 bool have_aclint; 56 RISCVVirtAIAType aia_type; 57 int aia_guests; 58 }; 59 60 enum { 61 VIRT_DEBUG, 62 VIRT_MROM, 63 VIRT_TEST, 64 VIRT_RTC, 65 VIRT_CLINT, 66 VIRT_ACLINT_SSWI, 67 VIRT_PLIC, 68 VIRT_APLIC_M, 69 VIRT_APLIC_S, 70 VIRT_UART0, 71 VIRT_VIRTIO, 72 VIRT_FW_CFG, 73 VIRT_IMSIC_M, 74 VIRT_IMSIC_S, 75 VIRT_FLASH, 76 VIRT_DRAM, 77 VIRT_PCIE_MMIO, 78 VIRT_PCIE_PIO, 79 VIRT_PCIE_ECAM 80 }; 81 82 enum { 83 UART0_IRQ = 10, 84 RTC_IRQ = 11, 85 VIRTIO_IRQ = 1, /* 1 to 8 */ 86 VIRTIO_COUNT = 8, 87 PCIE_IRQ = 0x20, /* 32 to 35 */ 88 VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */ 89 }; 90 91 #define VIRT_IRQCHIP_IPI_MSI 1 92 #define VIRT_IRQCHIP_NUM_MSIS 255 93 #define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV 94 #define VIRT_IRQCHIP_NUM_PRIO_BITS 3 95 #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3 96 #define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U) 97 98 #define VIRT_PLIC_PRIORITY_BASE 0x04 99 #define VIRT_PLIC_PENDING_BASE 0x1000 100 #define VIRT_PLIC_ENABLE_BASE 0x2000 101 #define VIRT_PLIC_ENABLE_STRIDE 0x80 102 #define VIRT_PLIC_CONTEXT_BASE 0x200000 103 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 104 #define VIRT_PLIC_SIZE(__num_context) \ 105 (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) 106 107 #define FDT_PCI_ADDR_CELLS 3 108 #define FDT_PCI_INT_CELLS 1 109 #define FDT_PLIC_INT_CELLS 1 110 #define FDT_APLIC_INT_CELLS 2 111 #define FDT_IMSIC_INT_CELLS 0 112 #define FDT_MAX_INT_CELLS 2 113 #define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 114 1 + FDT_MAX_INT_CELLS) 115 #define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 116 1 + FDT_PLIC_INT_CELLS) 117 #define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 118 1 + FDT_APLIC_INT_CELLS) 119 120 #endif 121