1 /* 2 * QEMU RISC-V VirtIO machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_RISCV_VIRT_H 20 #define HW_RISCV_VIRT_H 21 22 #include "hw/riscv/riscv_hart.h" 23 #include "hw/sysbus.h" 24 #include "hw/block/flash.h" 25 26 #define VIRT_CPUS_MAX 8 27 #define VIRT_SOCKETS_MAX 8 28 29 #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 30 #define RISCV_VIRT_MACHINE(obj) \ 31 OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_MACHINE) 32 33 typedef struct { 34 /*< private >*/ 35 MachineState parent; 36 37 /*< public >*/ 38 RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; 39 DeviceState *plic[VIRT_SOCKETS_MAX]; 40 PFlashCFI01 *flash[2]; 41 42 void *fdt; 43 int fdt_size; 44 } RISCVVirtState; 45 46 enum { 47 VIRT_DEBUG, 48 VIRT_MROM, 49 VIRT_TEST, 50 VIRT_RTC, 51 VIRT_CLINT, 52 VIRT_PLIC, 53 VIRT_UART0, 54 VIRT_VIRTIO, 55 VIRT_FLASH, 56 VIRT_DRAM, 57 VIRT_PCIE_MMIO, 58 VIRT_PCIE_PIO, 59 VIRT_PCIE_ECAM 60 }; 61 62 enum { 63 UART0_IRQ = 10, 64 RTC_IRQ = 11, 65 VIRTIO_IRQ = 1, /* 1 to 8 */ 66 VIRTIO_COUNT = 8, 67 PCIE_IRQ = 0x20, /* 32 to 35 */ 68 VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */ 69 }; 70 71 #define VIRT_PLIC_HART_CONFIG "MS" 72 #define VIRT_PLIC_NUM_SOURCES 127 73 #define VIRT_PLIC_NUM_PRIORITIES 7 74 #define VIRT_PLIC_PRIORITY_BASE 0x04 75 #define VIRT_PLIC_PENDING_BASE 0x1000 76 #define VIRT_PLIC_ENABLE_BASE 0x2000 77 #define VIRT_PLIC_ENABLE_STRIDE 0x80 78 #define VIRT_PLIC_CONTEXT_BASE 0x200000 79 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 80 #define VIRT_PLIC_SIZE(__num_context) \ 81 (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) 82 83 #define FDT_PCI_ADDR_CELLS 3 84 #define FDT_PCI_INT_CELLS 1 85 #define FDT_PLIC_ADDR_CELLS 0 86 #define FDT_PLIC_INT_CELLS 1 87 #define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \ 88 FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS) 89 90 #if defined(TARGET_RISCV32) 91 #define VIRT_CPU TYPE_RISCV_CPU_BASE32 92 #elif defined(TARGET_RISCV64) 93 #define VIRT_CPU TYPE_RISCV_CPU_BASE64 94 #endif 95 96 #endif 97