1 /* 2 * QEMU RISC-V VirtIO machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_RISCV_VIRT_H 20 #define HW_RISCV_VIRT_H 21 22 #include "hw/boards.h" 23 #include "hw/riscv/riscv_hart.h" 24 #include "hw/sysbus.h" 25 #include "hw/block/flash.h" 26 #include "hw/intc/riscv_imsic.h" 27 28 #define VIRT_CPUS_MAX_BITS 9 29 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) 30 #define VIRT_SOCKETS_MAX_BITS 2 31 #define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS) 32 33 #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 34 typedef struct RISCVVirtState RISCVVirtState; 35 DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE, 36 TYPE_RISCV_VIRT_MACHINE) 37 38 typedef enum RISCVVirtAIAType { 39 VIRT_AIA_TYPE_NONE = 0, 40 VIRT_AIA_TYPE_APLIC, 41 VIRT_AIA_TYPE_APLIC_IMSIC, 42 } RISCVVirtAIAType; 43 44 struct RISCVVirtState { 45 /*< private >*/ 46 MachineState parent; 47 48 /*< public >*/ 49 Notifier machine_done; 50 DeviceState *platform_bus_dev; 51 RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; 52 DeviceState *irqchip[VIRT_SOCKETS_MAX]; 53 PFlashCFI01 *flash[2]; 54 FWCfgState *fw_cfg; 55 56 int fdt_size; 57 bool have_aclint; 58 RISCVVirtAIAType aia_type; 59 int aia_guests; 60 char *oem_id; 61 char *oem_table_id; 62 OnOffAuto acpi; 63 const MemMapEntry *memmap; 64 struct GPEXHost *gpex_host; 65 }; 66 67 enum { 68 VIRT_DEBUG, 69 VIRT_MROM, 70 VIRT_TEST, 71 VIRT_RTC, 72 VIRT_CLINT, 73 VIRT_ACLINT_SSWI, 74 VIRT_PLIC, 75 VIRT_APLIC_M, 76 VIRT_APLIC_S, 77 VIRT_UART0, 78 VIRT_VIRTIO, 79 VIRT_FW_CFG, 80 VIRT_IMSIC_M, 81 VIRT_IMSIC_S, 82 VIRT_FLASH, 83 VIRT_DRAM, 84 VIRT_PCIE_MMIO, 85 VIRT_PCIE_PIO, 86 VIRT_PLATFORM_BUS, 87 VIRT_PCIE_ECAM 88 }; 89 90 enum { 91 UART0_IRQ = 10, 92 RTC_IRQ = 11, 93 VIRTIO_IRQ = 1, /* 1 to 8 */ 94 VIRTIO_COUNT = 8, 95 PCIE_IRQ = 0x20, /* 32 to 35 */ 96 VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 95 */ 97 }; 98 99 #define VIRT_PLATFORM_BUS_NUM_IRQS 32 100 101 #define VIRT_IRQCHIP_NUM_MSIS 255 102 #define VIRT_IRQCHIP_NUM_SOURCES 96 103 #define VIRT_IRQCHIP_NUM_PRIO_BITS 3 104 #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3 105 #define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U) 106 107 #define VIRT_PLIC_PRIORITY_BASE 0x00 108 #define VIRT_PLIC_PENDING_BASE 0x1000 109 #define VIRT_PLIC_ENABLE_BASE 0x2000 110 #define VIRT_PLIC_ENABLE_STRIDE 0x80 111 #define VIRT_PLIC_CONTEXT_BASE 0x200000 112 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 113 #define VIRT_PLIC_SIZE(__num_context) \ 114 (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) 115 116 #define FDT_PCI_ADDR_CELLS 3 117 #define FDT_PCI_INT_CELLS 1 118 #define FDT_PLIC_ADDR_CELLS 0 119 #define FDT_PLIC_INT_CELLS 1 120 #define FDT_APLIC_INT_CELLS 2 121 #define FDT_IMSIC_INT_CELLS 0 122 #define FDT_MAX_INT_CELLS 2 123 #define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 124 1 + FDT_MAX_INT_CELLS) 125 #define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 126 1 + FDT_PLIC_INT_CELLS) 127 #define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 128 1 + FDT_APLIC_INT_CELLS) 129 130 bool virt_is_acpi_enabled(RISCVVirtState *s); 131 void virt_acpi_setup(RISCVVirtState *vms); 132 uint32_t imsic_num_bits(uint32_t count); 133 134 /* 135 * The virt machine physical address space used by some of the devices 136 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, 137 * number of CPUs, and number of IMSIC guest files. 138 * 139 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, 140 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization 141 * of virt machine physical address space. 142 */ 143 144 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) 145 #if VIRT_IMSIC_GROUP_MAX_SIZE < \ 146 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) 147 #error "Can't accommodate single IMSIC group in address space" 148 #endif 149 150 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ 151 VIRT_IMSIC_GROUP_MAX_SIZE) 152 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE 153 #error "Can't accommodate all IMSIC groups in address space" 154 #endif 155 156 #endif 157