1 /* 2 * QEMU RISC-V VirtIO machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_RISCV_VIRT_H 20 #define HW_RISCV_VIRT_H 21 22 #include "hw/riscv/riscv_hart.h" 23 #include "hw/sysbus.h" 24 #include "hw/block/flash.h" 25 #include "qom/object.h" 26 27 #define VIRT_CPUS_MAX_BITS 9 28 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) 29 #define VIRT_SOCKETS_MAX_BITS 2 30 #define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS) 31 32 #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 33 typedef struct RISCVVirtState RISCVVirtState; 34 DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE, 35 TYPE_RISCV_VIRT_MACHINE) 36 37 typedef enum RISCVVirtAIAType { 38 VIRT_AIA_TYPE_NONE = 0, 39 VIRT_AIA_TYPE_APLIC, 40 VIRT_AIA_TYPE_APLIC_IMSIC, 41 } RISCVVirtAIAType; 42 43 struct RISCVVirtState { 44 /*< private >*/ 45 MachineState parent; 46 47 /*< public >*/ 48 Notifier machine_done; 49 DeviceState *platform_bus_dev; 50 RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; 51 DeviceState *irqchip[VIRT_SOCKETS_MAX]; 52 PFlashCFI01 *flash[2]; 53 FWCfgState *fw_cfg; 54 55 int fdt_size; 56 bool have_aclint; 57 RISCVVirtAIAType aia_type; 58 int aia_guests; 59 }; 60 61 enum { 62 VIRT_DEBUG, 63 VIRT_MROM, 64 VIRT_TEST, 65 VIRT_RTC, 66 VIRT_CLINT, 67 VIRT_ACLINT_SSWI, 68 VIRT_PLIC, 69 VIRT_APLIC_M, 70 VIRT_APLIC_S, 71 VIRT_UART0, 72 VIRT_VIRTIO, 73 VIRT_FW_CFG, 74 VIRT_IMSIC_M, 75 VIRT_IMSIC_S, 76 VIRT_FLASH, 77 VIRT_DRAM, 78 VIRT_PCIE_MMIO, 79 VIRT_PCIE_PIO, 80 VIRT_PLATFORM_BUS, 81 VIRT_PCIE_ECAM 82 }; 83 84 enum { 85 UART0_IRQ = 10, 86 RTC_IRQ = 11, 87 VIRTIO_IRQ = 1, /* 1 to 8 */ 88 VIRTIO_COUNT = 8, 89 PCIE_IRQ = 0x20, /* 32 to 35 */ 90 VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 96 */ 91 VIRTIO_NDEV = 96 /* Arbitrary maximum number of interrupts */ 92 }; 93 94 #define VIRT_PLATFORM_BUS_NUM_IRQS 32 95 96 #define VIRT_IRQCHIP_IPI_MSI 1 97 #define VIRT_IRQCHIP_NUM_MSIS 255 98 #define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV 99 #define VIRT_IRQCHIP_NUM_PRIO_BITS 3 100 #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3 101 #define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U) 102 103 #define VIRT_PLIC_PRIORITY_BASE 0x04 104 #define VIRT_PLIC_PENDING_BASE 0x1000 105 #define VIRT_PLIC_ENABLE_BASE 0x2000 106 #define VIRT_PLIC_ENABLE_STRIDE 0x80 107 #define VIRT_PLIC_CONTEXT_BASE 0x200000 108 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 109 #define VIRT_PLIC_SIZE(__num_context) \ 110 (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE) 111 112 #define FDT_PCI_ADDR_CELLS 3 113 #define FDT_PCI_INT_CELLS 1 114 #define FDT_PLIC_ADDR_CELLS 0 115 #define FDT_PLIC_INT_CELLS 1 116 #define FDT_APLIC_INT_CELLS 2 117 #define FDT_IMSIC_INT_CELLS 0 118 #define FDT_MAX_INT_CELLS 2 119 #define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 120 1 + FDT_MAX_INT_CELLS) 121 #define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 122 1 + FDT_PLIC_INT_CELLS) 123 #define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 124 1 + FDT_APLIC_INT_CELLS) 125 126 #endif 127