1 /* 2 * QEMU RISC-V VirtIO machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_RISCV_VIRT_H 20 #define HW_RISCV_VIRT_H 21 22 #include "hw/riscv/riscv_hart.h" 23 #include "hw/sysbus.h" 24 25 typedef struct { 26 /*< private >*/ 27 SysBusDevice parent_obj; 28 29 /*< public >*/ 30 RISCVHartArrayState soc; 31 DeviceState *plic; 32 void *fdt; 33 int fdt_size; 34 } RISCVVirtState; 35 36 enum { 37 VIRT_DEBUG, 38 VIRT_MROM, 39 VIRT_TEST, 40 VIRT_CLINT, 41 VIRT_PLIC, 42 VIRT_UART0, 43 VIRT_VIRTIO, 44 VIRT_DRAM, 45 VIRT_PCIE_MMIO, 46 VIRT_PCIE_PIO, 47 VIRT_PCIE_ECAM 48 }; 49 50 enum { 51 UART0_IRQ = 10, 52 VIRTIO_IRQ = 1, /* 1 to 8 */ 53 VIRTIO_COUNT = 8, 54 PCIE_IRQ = 0x20, /* 32 to 35 */ 55 VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */ 56 }; 57 58 #define VIRT_PLIC_HART_CONFIG "MS" 59 #define VIRT_PLIC_NUM_SOURCES 127 60 #define VIRT_PLIC_NUM_PRIORITIES 7 61 #define VIRT_PLIC_PRIORITY_BASE 0x04 62 #define VIRT_PLIC_PENDING_BASE 0x1000 63 #define VIRT_PLIC_ENABLE_BASE 0x2000 64 #define VIRT_PLIC_ENABLE_STRIDE 0x80 65 #define VIRT_PLIC_CONTEXT_BASE 0x200000 66 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 67 68 #define FDT_PCI_ADDR_CELLS 3 69 #define FDT_PCI_INT_CELLS 1 70 #define FDT_PLIC_ADDR_CELLS 0 71 #define FDT_PLIC_INT_CELLS 1 72 #define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \ 73 FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS) 74 75 #if defined(TARGET_RISCV32) 76 #define VIRT_CPU TYPE_RISCV_CPU_BASE32 77 #elif defined(TARGET_RISCV64) 78 #define VIRT_CPU TYPE_RISCV_CPU_BASE64 79 #endif 80 81 #endif 82