1 /* 2 * QEMU RISC-V VirtIO machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_RISCV_VIRT_H 20 #define HW_RISCV_VIRT_H 21 22 #include "hw/riscv/riscv_hart.h" 23 #include "hw/sysbus.h" 24 #include "hw/block/flash.h" 25 26 #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 27 #define RISCV_VIRT_MACHINE(obj) \ 28 OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_MACHINE) 29 30 typedef struct { 31 /*< private >*/ 32 MachineState parent; 33 34 /*< public >*/ 35 RISCVHartArrayState soc; 36 DeviceState *plic; 37 PFlashCFI01 *flash[2]; 38 39 void *fdt; 40 int fdt_size; 41 } RISCVVirtState; 42 43 enum { 44 VIRT_DEBUG, 45 VIRT_MROM, 46 VIRT_TEST, 47 VIRT_RTC, 48 VIRT_CLINT, 49 VIRT_PLIC, 50 VIRT_UART0, 51 VIRT_VIRTIO, 52 VIRT_FLASH, 53 VIRT_DRAM, 54 VIRT_PCIE_MMIO, 55 VIRT_PCIE_PIO, 56 VIRT_PCIE_ECAM 57 }; 58 59 enum { 60 UART0_IRQ = 10, 61 RTC_IRQ = 11, 62 VIRTIO_IRQ = 1, /* 1 to 8 */ 63 VIRTIO_COUNT = 8, 64 PCIE_IRQ = 0x20, /* 32 to 35 */ 65 VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */ 66 }; 67 68 #define VIRT_PLIC_HART_CONFIG "MS" 69 #define VIRT_PLIC_NUM_SOURCES 127 70 #define VIRT_PLIC_NUM_PRIORITIES 7 71 #define VIRT_PLIC_PRIORITY_BASE 0x04 72 #define VIRT_PLIC_PENDING_BASE 0x1000 73 #define VIRT_PLIC_ENABLE_BASE 0x2000 74 #define VIRT_PLIC_ENABLE_STRIDE 0x80 75 #define VIRT_PLIC_CONTEXT_BASE 0x200000 76 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 77 78 #define FDT_PCI_ADDR_CELLS 3 79 #define FDT_PCI_INT_CELLS 1 80 #define FDT_PLIC_ADDR_CELLS 0 81 #define FDT_PLIC_INT_CELLS 1 82 #define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \ 83 FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS) 84 85 #if defined(TARGET_RISCV32) 86 #define VIRT_CPU TYPE_RISCV_CPU_BASE32 87 #elif defined(TARGET_RISCV64) 88 #define VIRT_CPU TYPE_RISCV_CPU_BASE64 89 #endif 90 91 #endif 92