1 /* 2 * Spike machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_RISCV_SPIKE_H 20 #define HW_RISCV_SPIKE_H 21 22 #include "hw/riscv/riscv_hart.h" 23 #include "hw/sysbus.h" 24 25 typedef struct { 26 /*< private >*/ 27 SysBusDevice parent_obj; 28 29 /*< public >*/ 30 RISCVHartArrayState soc; 31 void *fdt; 32 int fdt_size; 33 } SpikeState; 34 35 enum { 36 SPIKE_MROM, 37 SPIKE_CLINT, 38 SPIKE_DRAM 39 }; 40 41 #if defined(TARGET_RISCV32) 42 #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1 43 #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 44 #elif defined(TARGET_RISCV64) 45 #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1 46 #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0 47 #endif 48 49 #endif 50