1 /* 2 * Spike machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_RISCV_SPIKE_H 20 #define HW_RISCV_SPIKE_H 21 22 #include "hw/riscv/riscv_hart.h" 23 #include "hw/sysbus.h" 24 25 #define SPIKE_CPUS_MAX 8 26 #define SPIKE_SOCKETS_MAX 8 27 28 #define TYPE_SPIKE_MACHINE MACHINE_TYPE_NAME("spike") 29 #define SPIKE_MACHINE(obj) \ 30 OBJECT_CHECK(SpikeState, (obj), TYPE_SPIKE_MACHINE) 31 32 typedef struct { 33 /*< private >*/ 34 MachineState parent; 35 36 /*< public >*/ 37 RISCVHartArrayState soc[SPIKE_SOCKETS_MAX]; 38 void *fdt; 39 int fdt_size; 40 } SpikeState; 41 42 enum { 43 SPIKE_MROM, 44 SPIKE_CLINT, 45 SPIKE_DRAM 46 }; 47 48 #if defined(TARGET_RISCV32) 49 #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32 50 #elif defined(TARGET_RISCV64) 51 #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64 52 #endif 53 54 #endif 55