1 /* 2 * Spike machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_SPIKE_H 20 #define HW_SPIKE_H 21 22 #define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1" 23 #define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10" 24 25 #define SPIKE(obj) \ 26 OBJECT_CHECK(SpikeState, (obj), TYPE_RISCV_SPIKE_BOARD) 27 28 typedef struct { 29 /*< private >*/ 30 SysBusDevice parent_obj; 31 32 /*< public >*/ 33 RISCVHartArrayState soc; 34 void *fdt; 35 int fdt_size; 36 } SpikeState; 37 38 39 enum { 40 SPIKE_MROM, 41 SPIKE_CLINT, 42 SPIKE_DRAM 43 }; 44 45 #if defined(TARGET_RISCV32) 46 #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1 47 #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 48 #elif defined(TARGET_RISCV64) 49 #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1 50 #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0 51 #endif 52 53 #endif 54