1*5b4beba1SMichael Clark /* 2*5b4beba1SMichael Clark * Spike machine interface 3*5b4beba1SMichael Clark * 4*5b4beba1SMichael Clark * Copyright (c) 2017 SiFive, Inc. 5*5b4beba1SMichael Clark * 6*5b4beba1SMichael Clark * This program is free software; you can redistribute it and/or modify it 7*5b4beba1SMichael Clark * under the terms and conditions of the GNU General Public License, 8*5b4beba1SMichael Clark * version 2 or later, as published by the Free Software Foundation. 9*5b4beba1SMichael Clark * 10*5b4beba1SMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 11*5b4beba1SMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12*5b4beba1SMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13*5b4beba1SMichael Clark * more details. 14*5b4beba1SMichael Clark * 15*5b4beba1SMichael Clark * You should have received a copy of the GNU General Public License along with 16*5b4beba1SMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 17*5b4beba1SMichael Clark */ 18*5b4beba1SMichael Clark 19*5b4beba1SMichael Clark #ifndef HW_SPIKE_H 20*5b4beba1SMichael Clark #define HW_SPIKE_H 21*5b4beba1SMichael Clark 22*5b4beba1SMichael Clark #define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1" 23*5b4beba1SMichael Clark #define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10" 24*5b4beba1SMichael Clark 25*5b4beba1SMichael Clark #define SPIKE(obj) \ 26*5b4beba1SMichael Clark OBJECT_CHECK(SpikeState, (obj), TYPE_RISCV_SPIKE_BOARD) 27*5b4beba1SMichael Clark 28*5b4beba1SMichael Clark typedef struct { 29*5b4beba1SMichael Clark /*< private >*/ 30*5b4beba1SMichael Clark SysBusDevice parent_obj; 31*5b4beba1SMichael Clark 32*5b4beba1SMichael Clark /*< public >*/ 33*5b4beba1SMichael Clark RISCVHartArrayState soc; 34*5b4beba1SMichael Clark void *fdt; 35*5b4beba1SMichael Clark int fdt_size; 36*5b4beba1SMichael Clark } SpikeState; 37*5b4beba1SMichael Clark 38*5b4beba1SMichael Clark 39*5b4beba1SMichael Clark enum { 40*5b4beba1SMichael Clark SPIKE_MROM, 41*5b4beba1SMichael Clark SPIKE_CLINT, 42*5b4beba1SMichael Clark SPIKE_DRAM 43*5b4beba1SMichael Clark }; 44*5b4beba1SMichael Clark 45*5b4beba1SMichael Clark #if defined(TARGET_RISCV32) 46*5b4beba1SMichael Clark #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1 47*5b4beba1SMichael Clark #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 48*5b4beba1SMichael Clark #elif defined(TARGET_RISCV64) 49*5b4beba1SMichael Clark #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1 50*5b4beba1SMichael Clark #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0 51*5b4beba1SMichael Clark #endif 52*5b4beba1SMichael Clark 53*5b4beba1SMichael Clark #endif 54