15b4beba1SMichael Clark /* 25b4beba1SMichael Clark * Spike machine interface 35b4beba1SMichael Clark * 45b4beba1SMichael Clark * Copyright (c) 2017 SiFive, Inc. 55b4beba1SMichael Clark * 65b4beba1SMichael Clark * This program is free software; you can redistribute it and/or modify it 75b4beba1SMichael Clark * under the terms and conditions of the GNU General Public License, 85b4beba1SMichael Clark * version 2 or later, as published by the Free Software Foundation. 95b4beba1SMichael Clark * 105b4beba1SMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 115b4beba1SMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 125b4beba1SMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 135b4beba1SMichael Clark * more details. 145b4beba1SMichael Clark * 155b4beba1SMichael Clark * You should have received a copy of the GNU General Public License along with 165b4beba1SMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 175b4beba1SMichael Clark */ 185b4beba1SMichael Clark 19*4996b128SMichael Clark #ifndef HW_RISCV_SPIKE_H 20*4996b128SMichael Clark #define HW_RISCV_SPIKE_H 215b4beba1SMichael Clark 225b4beba1SMichael Clark typedef struct { 235b4beba1SMichael Clark /*< private >*/ 245b4beba1SMichael Clark SysBusDevice parent_obj; 255b4beba1SMichael Clark 265b4beba1SMichael Clark /*< public >*/ 275b4beba1SMichael Clark RISCVHartArrayState soc; 285b4beba1SMichael Clark void *fdt; 295b4beba1SMichael Clark int fdt_size; 305b4beba1SMichael Clark } SpikeState; 315b4beba1SMichael Clark 325b4beba1SMichael Clark enum { 335b4beba1SMichael Clark SPIKE_MROM, 345b4beba1SMichael Clark SPIKE_CLINT, 355b4beba1SMichael Clark SPIKE_DRAM 365b4beba1SMichael Clark }; 375b4beba1SMichael Clark 382a8756edSMichael Clark enum { 392a8756edSMichael Clark SPIKE_CLOCK_FREQ = 1000000000 402a8756edSMichael Clark }; 412a8756edSMichael Clark 425b4beba1SMichael Clark #if defined(TARGET_RISCV32) 435b4beba1SMichael Clark #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1 445b4beba1SMichael Clark #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 455b4beba1SMichael Clark #elif defined(TARGET_RISCV64) 465b4beba1SMichael Clark #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1 475b4beba1SMichael Clark #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0 485b4beba1SMichael Clark #endif 495b4beba1SMichael Clark 505b4beba1SMichael Clark #endif 51