1 /* 2 * SiFive U series machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_SIFIVE_U_H 20 #define HW_SIFIVE_U_H 21 22 #define TYPE_SIFIVE_U "riscv.sifive_u" 23 24 #define SIFIVE_U(obj) \ 25 OBJECT_CHECK(SiFiveUState, (obj), TYPE_SIFIVE_U) 26 27 typedef struct SiFiveUState { 28 /*< private >*/ 29 SysBusDevice parent_obj; 30 31 /*< public >*/ 32 RISCVHartArrayState soc; 33 DeviceState *plic; 34 void *fdt; 35 int fdt_size; 36 } SiFiveUState; 37 38 enum { 39 SIFIVE_U_DEBUG, 40 SIFIVE_U_MROM, 41 SIFIVE_U_CLINT, 42 SIFIVE_U_PLIC, 43 SIFIVE_U_UART0, 44 SIFIVE_U_UART1, 45 SIFIVE_U_DRAM 46 }; 47 48 enum { 49 SIFIVE_U_UART0_IRQ = 3, 50 SIFIVE_U_UART1_IRQ = 4 51 }; 52 53 #define SIFIVE_U_PLIC_HART_CONFIG "MS" 54 #define SIFIVE_U_PLIC_NUM_SOURCES 127 55 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 56 #define SIFIVE_U_PLIC_PRIORITY_BASE 0x0 57 #define SIFIVE_U_PLIC_PENDING_BASE 0x1000 58 #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000 59 #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80 60 #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 61 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 62 63 #if defined(TARGET_RISCV32) 64 #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 65 #elif defined(TARGET_RISCV64) 66 #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 67 #endif 68 69 #endif 70