1 /* 2 * SiFive U series machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_SIFIVE_U_H 20 #define HW_SIFIVE_U_H 21 22 #include "hw/dma/sifive_pdma.h" 23 #include "hw/net/cadence_gem.h" 24 #include "hw/riscv/riscv_hart.h" 25 #include "hw/riscv/sifive_cpu.h" 26 #include "hw/gpio/sifive_gpio.h" 27 #include "hw/misc/sifive_u_otp.h" 28 #include "hw/misc/sifive_u_prci.h" 29 #include "hw/ssi/sifive_spi.h" 30 31 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" 32 #define RISCV_U_SOC(obj) \ 33 OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC) 34 35 typedef struct SiFiveUSoCState { 36 /*< private >*/ 37 DeviceState parent_obj; 38 39 /*< public >*/ 40 CPUClusterState e_cluster; 41 CPUClusterState u_cluster; 42 RISCVHartArrayState e_cpus; 43 RISCVHartArrayState u_cpus; 44 DeviceState *plic; 45 SiFiveUPRCIState prci; 46 SIFIVEGPIOState gpio; 47 SiFiveUOTPState otp; 48 SiFivePDMAState dma; 49 SiFiveSPIState spi0; 50 SiFiveSPIState spi2; 51 CadenceGEMState gem; 52 53 uint32_t serial; 54 char *cpu_type; 55 } SiFiveUSoCState; 56 57 #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") 58 #define RISCV_U_MACHINE(obj) \ 59 OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE) 60 61 typedef struct SiFiveUState { 62 /*< private >*/ 63 MachineState parent_obj; 64 65 /*< public >*/ 66 SiFiveUSoCState soc; 67 68 void *fdt; 69 int fdt_size; 70 71 bool start_in_flash; 72 uint32_t msel; 73 uint32_t serial; 74 } SiFiveUState; 75 76 enum { 77 SIFIVE_U_DEV_DEBUG, 78 SIFIVE_U_DEV_MROM, 79 SIFIVE_U_DEV_CLINT, 80 SIFIVE_U_DEV_L2CC, 81 SIFIVE_U_DEV_PDMA, 82 SIFIVE_U_DEV_L2LIM, 83 SIFIVE_U_DEV_PLIC, 84 SIFIVE_U_DEV_PRCI, 85 SIFIVE_U_DEV_UART0, 86 SIFIVE_U_DEV_UART1, 87 SIFIVE_U_DEV_GPIO, 88 SIFIVE_U_DEV_QSPI0, 89 SIFIVE_U_DEV_QSPI2, 90 SIFIVE_U_DEV_OTP, 91 SIFIVE_U_DEV_DMC, 92 SIFIVE_U_DEV_FLASH0, 93 SIFIVE_U_DEV_DRAM, 94 SIFIVE_U_DEV_GEM, 95 SIFIVE_U_DEV_GEM_MGMT 96 }; 97 98 enum { 99 SIFIVE_U_L2CC_IRQ0 = 1, 100 SIFIVE_U_L2CC_IRQ1 = 2, 101 SIFIVE_U_L2CC_IRQ2 = 3, 102 SIFIVE_U_UART0_IRQ = 4, 103 SIFIVE_U_UART1_IRQ = 5, 104 SIFIVE_U_QSPI2_IRQ = 6, 105 SIFIVE_U_GPIO_IRQ0 = 7, 106 SIFIVE_U_GPIO_IRQ1 = 8, 107 SIFIVE_U_GPIO_IRQ2 = 9, 108 SIFIVE_U_GPIO_IRQ3 = 10, 109 SIFIVE_U_GPIO_IRQ4 = 11, 110 SIFIVE_U_GPIO_IRQ5 = 12, 111 SIFIVE_U_GPIO_IRQ6 = 13, 112 SIFIVE_U_GPIO_IRQ7 = 14, 113 SIFIVE_U_GPIO_IRQ8 = 15, 114 SIFIVE_U_GPIO_IRQ9 = 16, 115 SIFIVE_U_GPIO_IRQ10 = 17, 116 SIFIVE_U_GPIO_IRQ11 = 18, 117 SIFIVE_U_GPIO_IRQ12 = 19, 118 SIFIVE_U_GPIO_IRQ13 = 20, 119 SIFIVE_U_GPIO_IRQ14 = 21, 120 SIFIVE_U_GPIO_IRQ15 = 22, 121 SIFIVE_U_PDMA_IRQ0 = 23, 122 SIFIVE_U_PDMA_IRQ1 = 24, 123 SIFIVE_U_PDMA_IRQ2 = 25, 124 SIFIVE_U_PDMA_IRQ3 = 26, 125 SIFIVE_U_PDMA_IRQ4 = 27, 126 SIFIVE_U_PDMA_IRQ5 = 28, 127 SIFIVE_U_PDMA_IRQ6 = 29, 128 SIFIVE_U_PDMA_IRQ7 = 30, 129 SIFIVE_U_QSPI0_IRQ = 51, 130 SIFIVE_U_GEM_IRQ = 53 131 }; 132 133 enum { 134 SIFIVE_U_HFCLK_FREQ = 33333333, 135 SIFIVE_U_RTCCLK_FREQ = 1000000 136 }; 137 138 enum { 139 MSEL_MEMMAP_QSPI0_FLASH = 1, 140 MSEL_L2LIM_QSPI0_FLASH = 6, 141 MSEL_L2LIM_QSPI2_SD = 11 142 }; 143 144 #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 145 #define SIFIVE_U_COMPUTE_CPU_COUNT 4 146 147 #define SIFIVE_U_PLIC_HART_CONFIG "MS" 148 #define SIFIVE_U_PLIC_NUM_SOURCES 54 149 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 150 #define SIFIVE_U_PLIC_PRIORITY_BASE 0x04 151 #define SIFIVE_U_PLIC_PENDING_BASE 0x1000 152 #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000 153 #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80 154 #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 155 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 156 157 #endif 158