1 /* 2 * SiFive U series machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_SIFIVE_U_H 20 #define HW_SIFIVE_U_H 21 22 #include "hw/net/cadence_gem.h" 23 #include "hw/riscv/riscv_hart.h" 24 #include "hw/riscv/sifive_cpu.h" 25 #include "hw/riscv/sifive_gpio.h" 26 #include "hw/riscv/sifive_u_prci.h" 27 #include "hw/riscv/sifive_u_otp.h" 28 29 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" 30 #define RISCV_U_SOC(obj) \ 31 OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC) 32 33 typedef struct SiFiveUSoCState { 34 /*< private >*/ 35 DeviceState parent_obj; 36 37 /*< public >*/ 38 CPUClusterState e_cluster; 39 CPUClusterState u_cluster; 40 RISCVHartArrayState e_cpus; 41 RISCVHartArrayState u_cpus; 42 DeviceState *plic; 43 SiFiveUPRCIState prci; 44 SIFIVEGPIOState gpio; 45 SiFiveUOTPState otp; 46 CadenceGEMState gem; 47 48 uint32_t serial; 49 } SiFiveUSoCState; 50 51 #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") 52 #define RISCV_U_MACHINE(obj) \ 53 OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE) 54 55 typedef struct SiFiveUState { 56 /*< private >*/ 57 MachineState parent_obj; 58 59 /*< public >*/ 60 SiFiveUSoCState soc; 61 62 void *fdt; 63 int fdt_size; 64 65 bool start_in_flash; 66 uint32_t msel; 67 uint32_t serial; 68 } SiFiveUState; 69 70 enum { 71 SIFIVE_U_DEBUG, 72 SIFIVE_U_MROM, 73 SIFIVE_U_CLINT, 74 SIFIVE_U_L2CC, 75 SIFIVE_U_L2LIM, 76 SIFIVE_U_PLIC, 77 SIFIVE_U_PRCI, 78 SIFIVE_U_UART0, 79 SIFIVE_U_UART1, 80 SIFIVE_U_GPIO, 81 SIFIVE_U_OTP, 82 SIFIVE_U_DMC, 83 SIFIVE_U_FLASH0, 84 SIFIVE_U_DRAM, 85 SIFIVE_U_GEM, 86 SIFIVE_U_GEM_MGMT 87 }; 88 89 enum { 90 SIFIVE_U_L2CC_IRQ0 = 1, 91 SIFIVE_U_L2CC_IRQ1 = 2, 92 SIFIVE_U_L2CC_IRQ2 = 3, 93 SIFIVE_U_UART0_IRQ = 4, 94 SIFIVE_U_UART1_IRQ = 5, 95 SIFIVE_U_GPIO_IRQ0 = 7, 96 SIFIVE_U_GPIO_IRQ1 = 8, 97 SIFIVE_U_GPIO_IRQ2 = 9, 98 SIFIVE_U_GPIO_IRQ3 = 10, 99 SIFIVE_U_GPIO_IRQ4 = 11, 100 SIFIVE_U_GPIO_IRQ5 = 12, 101 SIFIVE_U_GPIO_IRQ6 = 13, 102 SIFIVE_U_GPIO_IRQ7 = 14, 103 SIFIVE_U_GPIO_IRQ8 = 15, 104 SIFIVE_U_GPIO_IRQ9 = 16, 105 SIFIVE_U_GPIO_IRQ10 = 17, 106 SIFIVE_U_GPIO_IRQ11 = 18, 107 SIFIVE_U_GPIO_IRQ12 = 19, 108 SIFIVE_U_GPIO_IRQ13 = 20, 109 SIFIVE_U_GPIO_IRQ14 = 21, 110 SIFIVE_U_GPIO_IRQ15 = 22, 111 SIFIVE_U_GEM_IRQ = 0x35 112 }; 113 114 enum { 115 SIFIVE_U_HFCLK_FREQ = 33333333, 116 SIFIVE_U_RTCCLK_FREQ = 1000000 117 }; 118 119 enum { 120 MSEL_MEMMAP_QSPI0_FLASH = 1, 121 MSEL_L2LIM_QSPI0_FLASH = 6, 122 MSEL_L2LIM_QSPI2_SD = 11 123 }; 124 125 #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 126 #define SIFIVE_U_COMPUTE_CPU_COUNT 4 127 128 #define SIFIVE_U_PLIC_HART_CONFIG "MS" 129 #define SIFIVE_U_PLIC_NUM_SOURCES 54 130 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 131 #define SIFIVE_U_PLIC_PRIORITY_BASE 0x04 132 #define SIFIVE_U_PLIC_PENDING_BASE 0x1000 133 #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000 134 #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80 135 #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 136 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 137 138 #endif 139