xref: /openbmc/qemu/include/hw/riscv/sifive_u.h (revision b7bc6b18)
1 /*
2  * SiFive U series machine interface
3  *
4  * Copyright (c) 2017 SiFive, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2 or later, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 #ifndef HW_SIFIVE_U_H
20 #define HW_SIFIVE_U_H
21 
22 #include "hw/dma/sifive_pdma.h"
23 #include "hw/net/cadence_gem.h"
24 #include "hw/riscv/riscv_hart.h"
25 #include "hw/riscv/sifive_cpu.h"
26 #include "hw/gpio/sifive_gpio.h"
27 #include "hw/misc/sifive_u_otp.h"
28 #include "hw/misc/sifive_u_prci.h"
29 #include "hw/ssi/sifive_spi.h"
30 #include "hw/timer/sifive_pwm.h"
31 
32 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
33 #define RISCV_U_SOC(obj) \
34     OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
35 
36 typedef struct SiFiveUSoCState {
37     /*< private >*/
38     DeviceState parent_obj;
39 
40     /*< public >*/
41     CPUClusterState e_cluster;
42     CPUClusterState u_cluster;
43     RISCVHartArrayState e_cpus;
44     RISCVHartArrayState u_cpus;
45     DeviceState *plic;
46     SiFiveUPRCIState prci;
47     SIFIVEGPIOState gpio;
48     SiFiveUOTPState otp;
49     SiFivePDMAState dma;
50     SiFiveSPIState spi0;
51     SiFiveSPIState spi2;
52     CadenceGEMState gem;
53     SiFivePwmState pwm[2];
54 
55     uint32_t serial;
56     char *cpu_type;
57 } SiFiveUSoCState;
58 
59 #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
60 #define RISCV_U_MACHINE(obj) \
61     OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE)
62 
63 typedef struct SiFiveUState {
64     /*< private >*/
65     MachineState parent_obj;
66 
67     /*< public >*/
68     SiFiveUSoCState soc;
69 
70     void *fdt;
71     int fdt_size;
72 
73     bool start_in_flash;
74     uint32_t msel;
75     uint32_t serial;
76 } SiFiveUState;
77 
78 enum {
79     SIFIVE_U_DEV_DEBUG,
80     SIFIVE_U_DEV_MROM,
81     SIFIVE_U_DEV_CLINT,
82     SIFIVE_U_DEV_L2CC,
83     SIFIVE_U_DEV_PDMA,
84     SIFIVE_U_DEV_L2LIM,
85     SIFIVE_U_DEV_PLIC,
86     SIFIVE_U_DEV_PRCI,
87     SIFIVE_U_DEV_UART0,
88     SIFIVE_U_DEV_UART1,
89     SIFIVE_U_DEV_GPIO,
90     SIFIVE_U_DEV_QSPI0,
91     SIFIVE_U_DEV_QSPI2,
92     SIFIVE_U_DEV_OTP,
93     SIFIVE_U_DEV_DMC,
94     SIFIVE_U_DEV_FLASH0,
95     SIFIVE_U_DEV_DRAM,
96     SIFIVE_U_DEV_GEM,
97     SIFIVE_U_DEV_GEM_MGMT,
98     SIFIVE_U_DEV_PWM0,
99     SIFIVE_U_DEV_PWM1
100 };
101 
102 enum {
103     SIFIVE_U_L2CC_IRQ0 = 1,
104     SIFIVE_U_L2CC_IRQ1 = 2,
105     SIFIVE_U_L2CC_IRQ2 = 3,
106     SIFIVE_U_UART0_IRQ = 4,
107     SIFIVE_U_UART1_IRQ = 5,
108     SIFIVE_U_QSPI2_IRQ = 6,
109     SIFIVE_U_GPIO_IRQ0 = 7,
110     SIFIVE_U_GPIO_IRQ1 = 8,
111     SIFIVE_U_GPIO_IRQ2 = 9,
112     SIFIVE_U_GPIO_IRQ3 = 10,
113     SIFIVE_U_GPIO_IRQ4 = 11,
114     SIFIVE_U_GPIO_IRQ5 = 12,
115     SIFIVE_U_GPIO_IRQ6 = 13,
116     SIFIVE_U_GPIO_IRQ7 = 14,
117     SIFIVE_U_GPIO_IRQ8 = 15,
118     SIFIVE_U_GPIO_IRQ9 = 16,
119     SIFIVE_U_GPIO_IRQ10 = 17,
120     SIFIVE_U_GPIO_IRQ11 = 18,
121     SIFIVE_U_GPIO_IRQ12 = 19,
122     SIFIVE_U_GPIO_IRQ13 = 20,
123     SIFIVE_U_GPIO_IRQ14 = 21,
124     SIFIVE_U_GPIO_IRQ15 = 22,
125     SIFIVE_U_PDMA_IRQ0 = 23,
126     SIFIVE_U_PDMA_IRQ1 = 24,
127     SIFIVE_U_PDMA_IRQ2 = 25,
128     SIFIVE_U_PDMA_IRQ3 = 26,
129     SIFIVE_U_PDMA_IRQ4 = 27,
130     SIFIVE_U_PDMA_IRQ5 = 28,
131     SIFIVE_U_PDMA_IRQ6 = 29,
132     SIFIVE_U_PDMA_IRQ7 = 30,
133     SIFIVE_U_PWM0_IRQ0 = 42,
134     SIFIVE_U_PWM0_IRQ1 = 43,
135     SIFIVE_U_PWM0_IRQ2 = 44,
136     SIFIVE_U_PWM0_IRQ3 = 45,
137     SIFIVE_U_PWM1_IRQ0 = 46,
138     SIFIVE_U_PWM1_IRQ1 = 47,
139     SIFIVE_U_PWM1_IRQ2 = 48,
140     SIFIVE_U_PWM1_IRQ3 = 49,
141     SIFIVE_U_QSPI0_IRQ = 51,
142     SIFIVE_U_GEM_IRQ = 53
143 };
144 
145 enum {
146     SIFIVE_U_HFCLK_FREQ = 33333333,
147     SIFIVE_U_RTCCLK_FREQ = 1000000
148 };
149 
150 enum {
151     MSEL_MEMMAP_QSPI0_FLASH = 1,
152     MSEL_L2LIM_QSPI0_FLASH = 6,
153     MSEL_L2LIM_QSPI2_SD = 11
154 };
155 
156 #define SIFIVE_U_MANAGEMENT_CPU_COUNT   1
157 #define SIFIVE_U_COMPUTE_CPU_COUNT      4
158 
159 #define SIFIVE_U_PLIC_NUM_SOURCES 54
160 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7
161 #define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
162 #define SIFIVE_U_PLIC_PENDING_BASE 0x1000
163 #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
164 #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
165 #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000
166 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000
167 
168 #endif
169