1 /* 2 * SiFive U series machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_SIFIVE_U_H 20 #define HW_SIFIVE_U_H 21 22 typedef struct SiFiveUState { 23 /*< private >*/ 24 SysBusDevice parent_obj; 25 26 /*< public >*/ 27 RISCVHartArrayState soc; 28 DeviceState *plic; 29 void *fdt; 30 int fdt_size; 31 } SiFiveUState; 32 33 enum { 34 SIFIVE_U_DEBUG, 35 SIFIVE_U_MROM, 36 SIFIVE_U_CLINT, 37 SIFIVE_U_PLIC, 38 SIFIVE_U_UART0, 39 SIFIVE_U_UART1, 40 SIFIVE_U_DRAM 41 }; 42 43 enum { 44 SIFIVE_U_UART0_IRQ = 3, 45 SIFIVE_U_UART1_IRQ = 4 46 }; 47 48 enum { 49 SIFIVE_U_CLOCK_FREQ = 1000000000 50 }; 51 52 #define SIFIVE_U_PLIC_HART_CONFIG "MS" 53 #define SIFIVE_U_PLIC_NUM_SOURCES 127 54 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 55 #define SIFIVE_U_PLIC_PRIORITY_BASE 0x0 56 #define SIFIVE_U_PLIC_PENDING_BASE 0x1000 57 #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000 58 #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80 59 #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 60 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 61 62 #if defined(TARGET_RISCV32) 63 #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 64 #elif defined(TARGET_RISCV64) 65 #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 66 #endif 67 68 #endif 69