1 /* 2 * SiFive U series machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_SIFIVE_U_H 20 #define HW_SIFIVE_U_H 21 22 #include "hw/boards.h" 23 #include "hw/cpu/cluster.h" 24 #include "hw/dma/sifive_pdma.h" 25 #include "hw/net/cadence_gem.h" 26 #include "hw/riscv/riscv_hart.h" 27 #include "hw/riscv/sifive_cpu.h" 28 #include "hw/gpio/sifive_gpio.h" 29 #include "hw/misc/sifive_u_otp.h" 30 #include "hw/misc/sifive_u_prci.h" 31 #include "hw/ssi/sifive_spi.h" 32 #include "hw/timer/sifive_pwm.h" 33 34 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" 35 #define RISCV_U_SOC(obj) \ 36 OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC) 37 38 typedef struct SiFiveUSoCState { 39 /*< private >*/ 40 DeviceState parent_obj; 41 42 /*< public >*/ 43 CPUClusterState e_cluster; 44 CPUClusterState u_cluster; 45 RISCVHartArrayState e_cpus; 46 RISCVHartArrayState u_cpus; 47 DeviceState *plic; 48 SiFiveUPRCIState prci; 49 SIFIVEGPIOState gpio; 50 SiFiveUOTPState otp; 51 SiFivePDMAState dma; 52 SiFiveSPIState spi0; 53 SiFiveSPIState spi2; 54 CadenceGEMState gem; 55 SiFivePwmState pwm[2]; 56 57 uint32_t serial; 58 char *cpu_type; 59 } SiFiveUSoCState; 60 61 #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") 62 #define RISCV_U_MACHINE(obj) \ 63 OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE) 64 65 typedef struct SiFiveUState { 66 /*< private >*/ 67 MachineState parent_obj; 68 69 /*< public >*/ 70 SiFiveUSoCState soc; 71 72 bool start_in_flash; 73 uint32_t msel; 74 uint32_t serial; 75 } SiFiveUState; 76 77 enum { 78 SIFIVE_U_DEV_DEBUG, 79 SIFIVE_U_DEV_MROM, 80 SIFIVE_U_DEV_CLINT, 81 SIFIVE_U_DEV_L2CC, 82 SIFIVE_U_DEV_PDMA, 83 SIFIVE_U_DEV_L2LIM, 84 SIFIVE_U_DEV_PLIC, 85 SIFIVE_U_DEV_PRCI, 86 SIFIVE_U_DEV_UART0, 87 SIFIVE_U_DEV_UART1, 88 SIFIVE_U_DEV_GPIO, 89 SIFIVE_U_DEV_QSPI0, 90 SIFIVE_U_DEV_QSPI2, 91 SIFIVE_U_DEV_OTP, 92 SIFIVE_U_DEV_DMC, 93 SIFIVE_U_DEV_FLASH0, 94 SIFIVE_U_DEV_DRAM, 95 SIFIVE_U_DEV_GEM, 96 SIFIVE_U_DEV_GEM_MGMT, 97 SIFIVE_U_DEV_PWM0, 98 SIFIVE_U_DEV_PWM1 99 }; 100 101 enum { 102 SIFIVE_U_L2CC_IRQ0 = 1, 103 SIFIVE_U_L2CC_IRQ1 = 2, 104 SIFIVE_U_L2CC_IRQ2 = 3, 105 SIFIVE_U_UART0_IRQ = 4, 106 SIFIVE_U_UART1_IRQ = 5, 107 SIFIVE_U_QSPI2_IRQ = 6, 108 SIFIVE_U_GPIO_IRQ0 = 7, 109 SIFIVE_U_GPIO_IRQ1 = 8, 110 SIFIVE_U_GPIO_IRQ2 = 9, 111 SIFIVE_U_GPIO_IRQ3 = 10, 112 SIFIVE_U_GPIO_IRQ4 = 11, 113 SIFIVE_U_GPIO_IRQ5 = 12, 114 SIFIVE_U_GPIO_IRQ6 = 13, 115 SIFIVE_U_GPIO_IRQ7 = 14, 116 SIFIVE_U_GPIO_IRQ8 = 15, 117 SIFIVE_U_GPIO_IRQ9 = 16, 118 SIFIVE_U_GPIO_IRQ10 = 17, 119 SIFIVE_U_GPIO_IRQ11 = 18, 120 SIFIVE_U_GPIO_IRQ12 = 19, 121 SIFIVE_U_GPIO_IRQ13 = 20, 122 SIFIVE_U_GPIO_IRQ14 = 21, 123 SIFIVE_U_GPIO_IRQ15 = 22, 124 SIFIVE_U_PDMA_IRQ0 = 23, 125 SIFIVE_U_PDMA_IRQ1 = 24, 126 SIFIVE_U_PDMA_IRQ2 = 25, 127 SIFIVE_U_PDMA_IRQ3 = 26, 128 SIFIVE_U_PDMA_IRQ4 = 27, 129 SIFIVE_U_PDMA_IRQ5 = 28, 130 SIFIVE_U_PDMA_IRQ6 = 29, 131 SIFIVE_U_PDMA_IRQ7 = 30, 132 SIFIVE_U_PWM0_IRQ0 = 42, 133 SIFIVE_U_PWM0_IRQ1 = 43, 134 SIFIVE_U_PWM0_IRQ2 = 44, 135 SIFIVE_U_PWM0_IRQ3 = 45, 136 SIFIVE_U_PWM1_IRQ0 = 46, 137 SIFIVE_U_PWM1_IRQ1 = 47, 138 SIFIVE_U_PWM1_IRQ2 = 48, 139 SIFIVE_U_PWM1_IRQ3 = 49, 140 SIFIVE_U_QSPI0_IRQ = 51, 141 SIFIVE_U_GEM_IRQ = 53 142 }; 143 144 enum { 145 SIFIVE_U_HFCLK_FREQ = 33333333, 146 SIFIVE_U_RTCCLK_FREQ = 1000000 147 }; 148 149 enum { 150 MSEL_MEMMAP_QSPI0_FLASH = 1, 151 MSEL_L2LIM_QSPI0_FLASH = 6, 152 MSEL_L2LIM_QSPI2_SD = 11 153 }; 154 155 #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 156 #define SIFIVE_U_COMPUTE_CPU_COUNT 4 157 158 #define SIFIVE_U_PLIC_NUM_SOURCES 54 159 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 160 #define SIFIVE_U_PLIC_PRIORITY_BASE 0x00 161 #define SIFIVE_U_PLIC_PENDING_BASE 0x1000 162 #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000 163 #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80 164 #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 165 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 166 167 #endif 168