1 /* 2 * SiFive E series machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_SIFIVE_E_H 20 #define HW_SIFIVE_E_H 21 22 #include "hw/riscv/riscv_hart.h" 23 #include "hw/riscv/sifive_gpio.h" 24 25 #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" 26 #define RISCV_E_SOC(obj) \ 27 OBJECT_CHECK(SiFiveESoCState, (obj), TYPE_RISCV_E_SOC) 28 29 typedef struct SiFiveESoCState { 30 /*< private >*/ 31 SysBusDevice parent_obj; 32 33 /*< public >*/ 34 RISCVHartArrayState cpus; 35 DeviceState *plic; 36 SIFIVEGPIOState gpio; 37 MemoryRegion xip_mem; 38 MemoryRegion mask_rom; 39 } SiFiveESoCState; 40 41 typedef struct SiFiveEState { 42 /*< private >*/ 43 SysBusDevice parent_obj; 44 45 /*< public >*/ 46 SiFiveESoCState soc; 47 } SiFiveEState; 48 49 enum { 50 SIFIVE_E_DEBUG, 51 SIFIVE_E_MROM, 52 SIFIVE_E_OTP, 53 SIFIVE_E_CLINT, 54 SIFIVE_E_PLIC, 55 SIFIVE_E_AON, 56 SIFIVE_E_PRCI, 57 SIFIVE_E_OTP_CTRL, 58 SIFIVE_E_GPIO0, 59 SIFIVE_E_UART0, 60 SIFIVE_E_QSPI0, 61 SIFIVE_E_PWM0, 62 SIFIVE_E_UART1, 63 SIFIVE_E_QSPI1, 64 SIFIVE_E_PWM1, 65 SIFIVE_E_QSPI2, 66 SIFIVE_E_PWM2, 67 SIFIVE_E_XIP, 68 SIFIVE_E_DTIM 69 }; 70 71 enum { 72 SIFIVE_E_UART0_IRQ = 3, 73 SIFIVE_E_UART1_IRQ = 4, 74 SIFIVE_E_GPIO0_IRQ0 = 8 75 }; 76 77 #define SIFIVE_E_PLIC_HART_CONFIG "M" 78 #define SIFIVE_E_PLIC_NUM_SOURCES 127 79 #define SIFIVE_E_PLIC_NUM_PRIORITIES 7 80 #define SIFIVE_E_PLIC_PRIORITY_BASE 0x04 81 #define SIFIVE_E_PLIC_PENDING_BASE 0x1000 82 #define SIFIVE_E_PLIC_ENABLE_BASE 0x2000 83 #define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80 84 #define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000 85 #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000 86 87 #if defined(TARGET_RISCV32) 88 #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 89 #elif defined(TARGET_RISCV64) 90 #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 91 #endif 92 93 #endif 94