1 /* 2 * SiFive E series machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_SIFIVE_E_H 20 #define HW_SIFIVE_E_H 21 22 #include "hw/riscv/riscv_hart.h" 23 #include "hw/riscv/sifive_cpu.h" 24 #include "hw/gpio/sifive_gpio.h" 25 #include "hw/misc/sifive_e_aon.h" 26 #include "hw/boards.h" 27 28 #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" 29 #define RISCV_E_SOC(obj) \ 30 OBJECT_CHECK(SiFiveESoCState, (obj), TYPE_RISCV_E_SOC) 31 32 typedef struct SiFiveESoCState { 33 /*< private >*/ 34 DeviceState parent_obj; 35 36 /*< public >*/ 37 RISCVHartArrayState cpus; 38 DeviceState *plic; 39 SiFiveEAONState aon; 40 SIFIVEGPIOState gpio; 41 MemoryRegion xip_mem; 42 MemoryRegion mask_rom; 43 } SiFiveESoCState; 44 45 typedef struct SiFiveEState { 46 /*< private >*/ 47 MachineState parent_obj; 48 49 /*< public >*/ 50 SiFiveESoCState soc; 51 bool revb; 52 } SiFiveEState; 53 54 #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e") 55 #define RISCV_E_MACHINE(obj) \ 56 OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE) 57 58 enum { 59 SIFIVE_E_DEV_DEBUG, 60 SIFIVE_E_DEV_MROM, 61 SIFIVE_E_DEV_OTP, 62 SIFIVE_E_DEV_CLINT, 63 SIFIVE_E_DEV_PLIC, 64 SIFIVE_E_DEV_AON, 65 SIFIVE_E_DEV_PRCI, 66 SIFIVE_E_DEV_OTP_CTRL, 67 SIFIVE_E_DEV_GPIO0, 68 SIFIVE_E_DEV_UART0, 69 SIFIVE_E_DEV_QSPI0, 70 SIFIVE_E_DEV_PWM0, 71 SIFIVE_E_DEV_UART1, 72 SIFIVE_E_DEV_QSPI1, 73 SIFIVE_E_DEV_PWM1, 74 SIFIVE_E_DEV_QSPI2, 75 SIFIVE_E_DEV_PWM2, 76 SIFIVE_E_DEV_XIP, 77 SIFIVE_E_DEV_DTIM 78 }; 79 80 enum { 81 SIFIVE_E_AON_WDT_IRQ = 1, 82 SIFIVE_E_UART0_IRQ = 3, 83 SIFIVE_E_UART1_IRQ = 4, 84 SIFIVE_E_GPIO0_IRQ0 = 8 85 }; 86 87 #define SIFIVE_E_PLIC_HART_CONFIG "M" 88 /* 89 * Freedom E310 G002 and G003 supports 52 interrupt sources while 90 * Freedom E310 G000 supports 51 interrupt sources. We use the value 91 * of G002 and G003, so it is 53 (including interrupt source 0). 92 */ 93 #define SIFIVE_E_PLIC_NUM_SOURCES 53 94 #define SIFIVE_E_PLIC_NUM_PRIORITIES 7 95 #define SIFIVE_E_PLIC_PRIORITY_BASE 0x00 96 #define SIFIVE_E_PLIC_PENDING_BASE 0x1000 97 #define SIFIVE_E_PLIC_ENABLE_BASE 0x2000 98 #define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80 99 #define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000 100 #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000 101 102 #endif 103