1 /* 2 * SiFive E series machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_SIFIVE_E_H 20 #define HW_SIFIVE_E_H 21 22 #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" 23 #define RISCV_E_SOC(obj) \ 24 OBJECT_CHECK(SiFiveESoCState, (obj), TYPE_RISCV_E_SOC) 25 26 typedef struct SiFiveESoCState { 27 /*< private >*/ 28 SysBusDevice parent_obj; 29 30 /*< public >*/ 31 RISCVHartArrayState cpus; 32 DeviceState *plic; 33 } SiFiveESoCState; 34 35 typedef struct SiFiveEState { 36 /*< private >*/ 37 SysBusDevice parent_obj; 38 39 /*< public >*/ 40 SiFiveESoCState soc; 41 } SiFiveEState; 42 43 enum { 44 SIFIVE_E_DEBUG, 45 SIFIVE_E_MROM, 46 SIFIVE_E_OTP, 47 SIFIVE_E_CLINT, 48 SIFIVE_E_PLIC, 49 SIFIVE_E_AON, 50 SIFIVE_E_PRCI, 51 SIFIVE_E_OTP_CTRL, 52 SIFIVE_E_GPIO0, 53 SIFIVE_E_UART0, 54 SIFIVE_E_QSPI0, 55 SIFIVE_E_PWM0, 56 SIFIVE_E_UART1, 57 SIFIVE_E_QSPI1, 58 SIFIVE_E_PWM1, 59 SIFIVE_E_QSPI2, 60 SIFIVE_E_PWM2, 61 SIFIVE_E_XIP, 62 SIFIVE_E_DTIM 63 }; 64 65 enum { 66 SIFIVE_E_UART0_IRQ = 3, 67 SIFIVE_E_UART1_IRQ = 4 68 }; 69 70 #define SIFIVE_E_PLIC_HART_CONFIG "M" 71 #define SIFIVE_E_PLIC_NUM_SOURCES 127 72 #define SIFIVE_E_PLIC_NUM_PRIORITIES 7 73 #define SIFIVE_E_PLIC_PRIORITY_BASE 0x04 74 #define SIFIVE_E_PLIC_PENDING_BASE 0x1000 75 #define SIFIVE_E_PLIC_ENABLE_BASE 0x2000 76 #define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80 77 #define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000 78 #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000 79 80 #if defined(TARGET_RISCV32) 81 #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 82 #elif defined(TARGET_RISCV64) 83 #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 84 #endif 85 86 #endif 87