1 /* 2 * SiFive E series machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_SIFIVE_E_H 20 #define HW_SIFIVE_E_H 21 22 typedef struct SiFiveEState { 23 /*< private >*/ 24 SysBusDevice parent_obj; 25 26 /*< public >*/ 27 RISCVHartArrayState soc; 28 DeviceState *plic; 29 } SiFiveEState; 30 31 enum { 32 SIFIVE_E_DEBUG, 33 SIFIVE_E_MROM, 34 SIFIVE_E_OTP, 35 SIFIVE_E_CLINT, 36 SIFIVE_E_PLIC, 37 SIFIVE_E_AON, 38 SIFIVE_E_PRCI, 39 SIFIVE_E_OTP_CTRL, 40 SIFIVE_E_GPIO0, 41 SIFIVE_E_UART0, 42 SIFIVE_E_QSPI0, 43 SIFIVE_E_PWM0, 44 SIFIVE_E_UART1, 45 SIFIVE_E_QSPI1, 46 SIFIVE_E_PWM1, 47 SIFIVE_E_QSPI2, 48 SIFIVE_E_PWM2, 49 SIFIVE_E_XIP, 50 SIFIVE_E_DTIM 51 }; 52 53 enum { 54 SIFIVE_E_UART0_IRQ = 3, 55 SIFIVE_E_UART1_IRQ = 4 56 }; 57 58 #define SIFIVE_E_PLIC_HART_CONFIG "M" 59 #define SIFIVE_E_PLIC_NUM_SOURCES 127 60 #define SIFIVE_E_PLIC_NUM_PRIORITIES 7 61 #define SIFIVE_E_PLIC_PRIORITY_BASE 0x0 62 #define SIFIVE_E_PLIC_PENDING_BASE 0x1000 63 #define SIFIVE_E_PLIC_ENABLE_BASE 0x2000 64 #define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80 65 #define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000 66 #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000 67 68 #if defined(TARGET_RISCV32) 69 #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 70 #elif defined(TARGET_RISCV64) 71 #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 72 #endif 73 74 #endif 75