1 /* 2 * SiFive E series machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_SIFIVE_E_H 20 #define HW_SIFIVE_E_H 21 22 #define TYPE_SIFIVE_E "riscv.sifive_e" 23 24 #define SIFIVE_E(obj) \ 25 OBJECT_CHECK(SiFiveEState, (obj), TYPE_SIFIVE_E) 26 27 typedef struct SiFiveEState { 28 /*< private >*/ 29 SysBusDevice parent_obj; 30 31 /*< public >*/ 32 RISCVHartArrayState soc; 33 DeviceState *plic; 34 } SiFiveEState; 35 36 enum { 37 SIFIVE_E_DEBUG, 38 SIFIVE_E_MROM, 39 SIFIVE_E_OTP, 40 SIFIVE_E_CLINT, 41 SIFIVE_E_PLIC, 42 SIFIVE_E_AON, 43 SIFIVE_E_PRCI, 44 SIFIVE_E_OTP_CTRL, 45 SIFIVE_E_GPIO0, 46 SIFIVE_E_UART0, 47 SIFIVE_E_QSPI0, 48 SIFIVE_E_PWM0, 49 SIFIVE_E_UART1, 50 SIFIVE_E_QSPI1, 51 SIFIVE_E_PWM1, 52 SIFIVE_E_QSPI2, 53 SIFIVE_E_PWM2, 54 SIFIVE_E_XIP, 55 SIFIVE_E_DTIM 56 }; 57 58 enum { 59 SIFIVE_E_UART0_IRQ = 3, 60 SIFIVE_E_UART1_IRQ = 4 61 }; 62 63 #define SIFIVE_E_PLIC_HART_CONFIG "M" 64 #define SIFIVE_E_PLIC_NUM_SOURCES 127 65 #define SIFIVE_E_PLIC_NUM_PRIORITIES 7 66 #define SIFIVE_E_PLIC_PRIORITY_BASE 0x0 67 #define SIFIVE_E_PLIC_PENDING_BASE 0x1000 68 #define SIFIVE_E_PLIC_ENABLE_BASE 0x2000 69 #define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80 70 #define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000 71 #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000 72 73 #if defined(TARGET_RISCV32) 74 #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 75 #elif defined(TARGET_RISCV64) 76 #define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 77 #endif 78 79 #endif 80